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119 lines
3.4 KiB
C
119 lines
3.4 KiB
C
/* Copyright (C) 2012-2024 Free Software Foundation, Inc.
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Contributed by Altera and Mentor Graphics, Inc.
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This file is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 3, or (at your option) any
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later version.
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This file is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#include "lib2-gcn.h"
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/* 8-bit V64QI divide and modulo as used in gcn.
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This is a simple conversion from lib2-divmod.c. */
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#define MASKMODE v64qi
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#include "amdgcn_veclib.h"
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static v64udi
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__udivmodv64qi4_aux (v64uqi num, v64uqi den, v64qi __mask)
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{
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v64uqi bit = VECTOR_INIT ((unsigned char)1U);
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v64uqi res = VECTOR_INIT ((unsigned char)0U);
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VECTOR_WHILE ((den < num) & (bit != 0) & ((den & (1<<7)) == 0),
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cond, NO_COND)
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VECTOR_COND_MOVE (den, den << 1, cond);
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VECTOR_COND_MOVE (bit, bit << 1, cond);
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VECTOR_ENDWHILE
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VECTOR_WHILE (bit != 0, loopcond, NO_COND)
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VECTOR_IF2 (num >= den, ifcond, loopcond)
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VECTOR_COND_MOVE (num, num - den, ifcond);
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VECTOR_COND_MOVE (res, res | bit, ifcond);
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VECTOR_ENDIF
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VECTOR_COND_MOVE (bit, bit >> 1, loopcond);
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VECTOR_COND_MOVE (den, den >> 1, loopcond);
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VECTOR_ENDWHILE
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return PACK_SI_PAIR (res, num);
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}
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static v64udi
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__divmodv64qi4_aux (v64qi a, v64qi b, v64qi __mask)
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{
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v64qi nega = VECTOR_INIT ((char)0);
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v64qi negb = VECTOR_INIT ((char)0);
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VECTOR_IF (a < 0, cond)
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VECTOR_COND_MOVE (a, -a, cond);
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nega = cond;
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VECTOR_ENDIF
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VECTOR_IF (b < 0, cond)
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VECTOR_COND_MOVE (b, -b, cond);
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negb = cond;
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VECTOR_ENDIF
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v64uqi ua = __builtin_convertvector (a, v64uqi);
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v64uqi ub = __builtin_convertvector (b, v64uqi);
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v64udi pair = __udivmodv64qi4_aux (ua, ub, __mask);
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v64qi quot = UNPACK_SI_LOW (v64qi, pair);
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v64qi rem = UNPACK_SI_HIGH (v64qi, pair);
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VECTOR_COND_MOVE (quot, -quot, nega ^ negb);
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VECTOR_COND_MOVE (rem, -rem, nega);
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pair = PACK_SI_PAIR (quot, rem);
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return pair;
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}
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static inline v64qi
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__divv64qi3_aux (v64qi a, v64qi b, v64qi __mask)
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{
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v64udi pair = __divmodv64qi4_aux (a, b, __mask);
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return UNPACK_SI_LOW (v64qi, pair);
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}
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static inline v64qi
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__modv64qi3_aux (v64qi a, v64qi b, v64qi __mask)
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{
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v64udi pair = __divmodv64qi4_aux (a, b, __mask);
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return UNPACK_SI_HIGH (v64qi, pair);
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}
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static inline v64uqi
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__udivv64qi3_aux (v64uqi a, v64uqi b, v64qi __mask)
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{
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v64udi pair = __udivmodv64qi4_aux (a, b, __mask);
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return UNPACK_SI_LOW (v64uqi, pair);
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}
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static inline v64uqi
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__umodv64qi3_aux (v64uqi a, v64uqi b, v64qi __mask)
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{
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v64udi pair = __udivmodv64qi4_aux (a, b, __mask);
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return UNPACK_SI_HIGH (v64uqi, pair);
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}
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DEF_VARIANTS (__div, qi3, qi)
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DEF_VARIANTS (__mod, qi3, qi)
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DEF_VARIANTS_B (__divmod, qi4, udi, qi)
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DEF_VARIANTS (__udiv, qi3, uqi)
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DEF_VARIANTS (__umod, qi3, uqi)
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DEF_VARIANTS_B (__udivmod, qi4, udi, uqi)
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