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92b3138b83
Updated dependencies: * GMP 6.2.1 * ISL 0.24 * MPL 1.2.1 * MPFR 4.1.0 The dependencies were pulled in by running the ./contrib/download_prerequisites script and then manually removing the symbolic links and archives, and renaming the directories (i.e mv isl-0.24 to isl)
40 lines
1.6 KiB
C
40 lines
1.6 KiB
C
/* Store register values as _Unwind_Word type in DWARF2 EH unwind context.
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Copyright (C) 2023 Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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/* Return the value of the VLENB register. This should only be
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called if we know this is an vector extension enabled RISC-V host. */
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static inline long
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riscv_vlenb (void)
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{
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register long vlenb asm ("a0");
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/* 0xc2202573 == csrr a0, 0xc22 */
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asm (".insn 0xc2202573" : "=r"(vlenb));
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return vlenb;
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}
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/* Lazily provide a value for VLENB, so that we don't try to execute RVV
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instructions unless we know they're needed. */
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#define DWARF_LAZY_REGISTER_VALUE(REGNO, VALUE) \
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((REGNO) == RISCV_DWARF_VLENB && ((*VALUE) = riscv_vlenb (), 1))
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