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f133d007f9
Old version was from 2012-05-06, 6.1.2 is from 2016-12-16 A lot of support for newer processors and speedups since then See gmp/NEWS for details
60 lines
2.0 KiB
NASM
60 lines
2.0 KiB
NASM
dnl Alpha time stamp counter access routine.
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dnl Copyright 2000, 2005 Free Software Foundation, Inc.
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or modify
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dnl it under the terms of either:
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dnl
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dnl * the GNU Lesser General Public License as published by the Free
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dnl Software Foundation; either version 3 of the License, or (at your
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dnl option) any later version.
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dnl
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dnl or
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dnl
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dnl * the GNU General Public License as published by the Free Software
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dnl Foundation; either version 2 of the License, or (at your option) any
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dnl later version.
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dnl
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dnl or both in parallel, as here.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful, but
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dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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dnl for more details.
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dnl
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dnl You should have received copies of the GNU General Public License and the
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dnl GNU Lesser General Public License along with the GNU MP Library. If not,
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dnl see https://www.gnu.org/licenses/.
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include(`../config.m4')
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C void speed_cyclecounter (unsigned int p[2]);
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C
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C The rpcc instruction returns a 64-bit value split into two 32-bit fields.
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C The lower 32 bits are set by the hardware, and the upper 32 bits are set
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C by the operating system. The real per-process cycle count is the sum of
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C these halves.
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C Unfortunately, some operating systems don't get this right. NetBSD 1.3 is
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C known to sometimes put garbage in the upper half. Whether newer NetBSD
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C versions get it right, is unknown to us.
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C rpcc measures cycles elapsed in the user program and hence should be very
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C accurate even on a busy system. Losing cache contents due to task
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C switching may have an effect though.
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ASM_START()
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PROLOGUE(speed_cyclecounter)
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rpcc r0
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srl r0,32,r1
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addq r1,r0,r0
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stl r0,0(r16)
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stl r31,4(r16) C zero upper return word
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ret r31,(r26),1
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EPILOGUE(speed_cyclecounter)
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ASM_END()
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