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f133d007f9
Old version was from 2012-05-06, 6.1.2 is from 2016-12-16 A lot of support for newer processors and speedups since then See gmp/NEWS for details
172 lines
3.9 KiB
NASM
172 lines
3.9 KiB
NASM
dnl AMD64 mpn_modexact_1_odd -- Hensel norm remainder.
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dnl Copyright 2000-2006, 2011, 2012 Free Software Foundation, Inc.
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or modify
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dnl it under the terms of either:
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dnl
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dnl * the GNU Lesser General Public License as published by the Free
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dnl Software Foundation; either version 3 of the License, or (at your
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dnl option) any later version.
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dnl
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dnl or
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dnl
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dnl * the GNU General Public License as published by the Free Software
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dnl Foundation; either version 2 of the License, or (at your option) any
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dnl later version.
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dnl
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dnl or both in parallel, as here.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful, but
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dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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dnl for more details.
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dnl
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dnl You should have received copies of the GNU General Public License and the
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dnl GNU Lesser General Public License along with the GNU MP Library. If not,
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dnl see https://www.gnu.org/licenses/.
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include(`../config.m4')
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C cycles/limb
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C AMD K8,K9 10
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C AMD K10 10
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C Intel P4 33
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C Intel core2 13
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C Intel corei 14.5
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C Intel atom 35
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C VIA nano ?
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C The dependent chain in the main loop is
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C
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C cycles
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C sub %rdx, %rax 1
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C imul %r9, %rax 4
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C mul %r8 5
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C ----
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C total 10
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C
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C The mov load from src seems to need to be scheduled back before the jz to
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C achieve this speed, out-of-order execution apparently can't completely hide
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C the latency otherwise.
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C
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C The l=src[i]-cbit step is rotated back too, since that allows us to avoid it
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C for the first iteration (where there's no cbit).
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C
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C The code alignment used (32-byte) for the loop also seems necessary. Without
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C that the non-PIC case has adc crossing the 0x60 offset, apparently making it
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C run at 11 cycles instead of 10.
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ABI_SUPPORT(DOS64)
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ABI_SUPPORT(STD64)
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ASM_START()
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TEXT
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ALIGN(32)
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PROLOGUE(mpn_modexact_1_odd)
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FUNC_ENTRY(3)
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mov $0, R32(%rcx)
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IFDOS(` jmp L(ent) ')
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PROLOGUE(mpn_modexact_1c_odd)
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FUNC_ENTRY(4)
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L(ent):
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C rdi src
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C rsi size
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C rdx divisor
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C rcx carry
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mov %rdx, %r8 C d
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shr R32(%rdx) C d/2
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LEA( binvert_limb_table, %r9)
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and $127, R32(%rdx)
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mov %rcx, %r10 C initial carry
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movzbl (%r9,%rdx), R32(%rdx) C inv 8 bits
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mov (%rdi), %rax C src[0]
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lea (%rdi,%rsi,8), %r11 C src end
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mov %r8, %rdi C d, made available to imull
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lea (%rdx,%rdx), R32(%rcx) C 2*inv
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imul R32(%rdx), R32(%rdx) C inv*inv
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neg %rsi C -size
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imul R32(%rdi), R32(%rdx) C inv*inv*d
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sub R32(%rdx), R32(%rcx) C inv = 2*inv - inv*inv*d, 16 bits
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lea (%rcx,%rcx), R32(%rdx) C 2*inv
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imul R32(%rcx), R32(%rcx) C inv*inv
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imul R32(%rdi), R32(%rcx) C inv*inv*d
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sub R32(%rcx), R32(%rdx) C inv = 2*inv - inv*inv*d, 32 bits
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xor R32(%rcx), R32(%rcx) C initial cbit
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lea (%rdx,%rdx), %r9 C 2*inv
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imul %rdx, %rdx C inv*inv
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imul %r8, %rdx C inv*inv*d
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sub %rdx, %r9 C inv = 2*inv - inv*inv*d, 64 bits
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mov %r10, %rdx C initial climb
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ASSERT(e,` C d*inv == 1 mod 2^64
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mov %r8, %r10
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imul %r9, %r10
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cmp $1, %r10')
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inc %rsi
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jz L(one)
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ALIGN(16)
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L(top):
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C rax l = src[i]-cbit
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C rcx new cbit, 0 or 1
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C rdx climb, high of last product
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C rsi counter, limbs, negative
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C rdi
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C r8 divisor
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C r9 inverse
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C r11 src end ptr
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sub %rdx, %rax C l = src[i]-cbit - climb
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adc $0, %rcx C more cbit
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imul %r9, %rax C q = l * inverse
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mul %r8 C climb = high (q * d)
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mov (%r11,%rsi,8), %rax C src[i+1]
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sub %rcx, %rax C next l = src[i+1] - cbit
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setc R8(%rcx) C new cbit
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inc %rsi
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jnz L(top)
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L(one):
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sub %rdx, %rax C l = src[i]-cbit - climb
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adc $0, %rcx C more cbit
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imul %r9, %rax C q = l * inverse
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mul %r8 C climb = high (q * d)
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lea (%rcx,%rdx), %rax C climb+cbit
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FUNC_EXIT()
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ret
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EPILOGUE(mpn_modexact_1c_odd)
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EPILOGUE(mpn_modexact_1_odd)
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