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f133d007f9
Old version was from 2012-05-06, 6.1.2 is from 2016-12-16 A lot of support for newer processors and speedups since then See gmp/NEWS for details
177 lines
3.8 KiB
NASM
177 lines
3.8 KiB
NASM
dnl AMD64 mpn_addlsh_n and mpn_rsblsh_n. R = V2^k +- U.
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dnl Copyright 2006, 2010-2012 Free Software Foundation, Inc.
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or modify
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dnl it under the terms of either:
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dnl
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dnl * the GNU Lesser General Public License as published by the Free
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dnl Software Foundation; either version 3 of the License, or (at your
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dnl option) any later version.
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dnl
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dnl or
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dnl
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dnl * the GNU General Public License as published by the Free Software
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dnl Foundation; either version 2 of the License, or (at your option) any
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dnl later version.
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dnl
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dnl or both in parallel, as here.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful, but
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dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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dnl for more details.
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dnl
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dnl You should have received copies of the GNU General Public License and the
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dnl GNU Lesser General Public License along with the GNU MP Library. If not,
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dnl see https://www.gnu.org/licenses/.
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include(`../config.m4')
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C cycles/limb
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C AMD K8,K9 3.1 < 3.85 for lshift + add_n
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C AMD K10 3.1 < 3.85 for lshift + add_n
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C Intel P4 14.6 > 7.33 for lshift + add_n
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C Intel core2 3.87 > 3.27 for lshift + add_n
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C Intel NHM 4 > 3.75 for lshift + add_n
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C Intel SBR (5.8) > 3.46 for lshift + add_n
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C Intel atom (7.75) < 8.75 for lshift + add_n
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C VIA nano 4.7 < 6.25 for lshift + add_n
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C This was written quickly and not optimized at all. Surely one could get
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C closer to 3 c/l or perhaps even under 3 c/l. Ideas:
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C 1) Use indexing to save the 3 LEA
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C 2) Write reasonable feed-in code
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C 3) Be more clever about register usage
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C 4) Unroll more, handling CL negation, carry save/restore cost much now
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C 5) Reschedule
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C INPUT PARAMETERS
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define(`rp', `%rdi')
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define(`up', `%rsi')
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define(`vp', `%rdx')
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define(`n', `%rcx')
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define(`cnt', `%r8')
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ifdef(`OPERATION_addlsh_n',`
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define(ADCSBB, `adc')
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define(func, mpn_addlsh_n)
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')
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ifdef(`OPERATION_rsblsh_n',`
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define(ADCSBB, `sbb')
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define(func, mpn_rsblsh_n)
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')
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MULFUNC_PROLOGUE(mpn_addlsh_n mpn_rsblsh_n)
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ABI_SUPPORT(DOS64)
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ABI_SUPPORT(STD64)
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ASM_START()
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TEXT
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ALIGN(16)
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PROLOGUE(func)
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FUNC_ENTRY(4)
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IFDOS(` mov 56(%rsp), %r8d ')
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push %r12
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push %r13
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push %r14
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push %rbp
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push %rbx
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mov n, %rax
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xor R32(%rbx), R32(%rbx) C clear carry save register
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mov R32(%r8), R32(%rcx) C shift count
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xor R32(%rbp), R32(%rbp) C limb carry
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mov R32(%rax), R32(%r11)
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and $3, R32(%r11)
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je L(4)
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sub $1, R32(%r11)
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L(012): mov (vp), %r8
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mov %r8, %r12
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shl R8(%rcx), %r8
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or %rbp, %r8
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neg R8(%rcx)
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mov %r12, %rbp
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shr R8(%rcx), %rbp
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neg R8(%rcx)
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add R32(%rbx), R32(%rbx)
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ADCSBB (up), %r8
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mov %r8, (rp)
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sbb R32(%rbx), R32(%rbx)
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lea 8(up), up
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lea 8(vp), vp
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lea 8(rp), rp
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sub $1, R32(%r11)
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jnc L(012)
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L(4): sub $4, %rax
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jc L(end)
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ALIGN(16)
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L(top): mov (vp), %r8
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mov %r8, %r12
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mov 8(vp), %r9
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mov %r9, %r13
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mov 16(vp), %r10
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mov %r10, %r14
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mov 24(vp), %r11
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shl R8(%rcx), %r8
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shl R8(%rcx), %r9
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shl R8(%rcx), %r10
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or %rbp, %r8
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mov %r11, %rbp
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shl R8(%rcx), %r11
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neg R8(%rcx)
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shr R8(%rcx), %r12
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shr R8(%rcx), %r13
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shr R8(%rcx), %r14
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shr R8(%rcx), %rbp C used next iteration
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or %r12, %r9
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or %r13, %r10
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or %r14, %r11
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neg R8(%rcx)
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add R32(%rbx), R32(%rbx) C restore carry flag
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ADCSBB (up), %r8
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ADCSBB 8(up), %r9
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ADCSBB 16(up), %r10
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ADCSBB 24(up), %r11
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mov %r8, (rp)
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mov %r9, 8(rp)
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mov %r10, 16(rp)
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mov %r11, 24(rp)
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sbb R32(%rbx), R32(%rbx) C save carry flag
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lea 32(up), up
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lea 32(vp), vp
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lea 32(rp), rp
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sub $4, %rax
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jnc L(top)
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L(end): add R32(%rbx), R32(%rbx)
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ADCSBB $0, %rbp
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mov %rbp, %rax
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pop %rbx
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pop %rbp
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pop %r14
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pop %r13
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pop %r12
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FUNC_EXIT()
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ret
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EPILOGUE()
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