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Old version was from 2012-05-06, 6.1.2 is from 2016-12-16 A lot of support for newer processors and speedups since then See gmp/NEWS for details
282 lines
9.2 KiB
Plaintext
282 lines
9.2 KiB
Plaintext
Copyright 2000-2005 Free Software Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify
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it under the terms of either:
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* the GNU Lesser General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your
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option) any later version.
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or
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* the GNU General Public License as published by the Free Software
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Foundation; either version 2 of the License, or (at your option) any
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later version.
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or both in parallel, as here.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received copies of the GNU General Public License and the
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GNU Lesser General Public License along with the GNU MP Library. If not,
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see https://www.gnu.org/licenses/.
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IA-64 MPN SUBROUTINES
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This directory contains mpn functions for the IA-64 architecture.
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CODE ORGANIZATION
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mpn/ia64 itanium-2, and generic ia64
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The code here has been optimized primarily for Itanium 2. Very few Itanium 1
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chips were ever sold, and Itanium 2 is more powerful, so the latter is what
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we concentrate on.
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CHIP NOTES
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The IA-64 ISA keeps instructions three and three in 128 bit bundles.
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Programmers/compilers need to put explicit breaks `;;' when there are WAW or
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RAW dependencies, with some notable exceptions. Such "breaks" are typically
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at the end of a bundle, but can be put between operations within some bundle
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types too.
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The Itanium 1 and Itanium 2 implementations can under ideal conditions
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execute two bundles per cycle. The Itanium 1 allows 4 of these instructions
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to do integer operations, while the Itanium 2 allows all 6 to be integer
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operations.
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Taken cloop branches seem to insert a bubble into the pipeline most of the
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time on Itanium 1.
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Loads to the fp registers bypass the L1 cache and thus get extremely long
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latencies, 9 cycles on the Itanium 1 and 6 cycles on the Itanium 2.
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The software pipeline stuff using br.ctop instruction causes delays, since
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many issue slots are taken up by instructions with zero predicates, and
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since many extra instructions are needed to set things up. These features
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are clearly designed for code density, not speed.
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Misc pipeline limitations (Itanium 1):
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* The getf.sig instruction can only execute in M0.
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* At most four integer instructions/cycle.
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* Nops take up resources like any plain instructions.
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Misc pipeline limitations (Itanium 2):
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* The getf.sig instruction can only execute in M0.
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* Nops take up resources like any plain instructions.
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ASSEMBLY SYNTAX
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.align pads with nops in a text segment, but gas 2.14 and earlier
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incorrectly byte-swaps its nop bundle in big endian mode (eg. hpux), making
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it come out as break instructions. We use the ALIGN() macro in
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mpn/ia64/ia64-defs.m4 when it might be executed across. That macro
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suppresses any .align if the problem is detected by configure. Lack of
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alignment might hurt performance but will at least be correct.
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foo:: to create a global symbol is not accepted by gas. Use separate
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".global foo" and "foo:" instead.
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.global is the standard global directive. gas accepts .globl, but hpux "as"
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doesn't.
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.proc / .endp generates the appropriate .type and .size information for ELF,
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so the latter directives don't need to be given explicitly.
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.pred.rel "mutex"... is standard for annotating predicate register
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relationships. gas also accepts .pred.rel.mutex, but hpux "as" doesn't.
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.pred directives can't be put on a line with a label, like
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".Lfoo: .pred ...", the HP assembler on HP-UX 11.23 rejects that.
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gas is happy with it, and past versions of HP had seemed ok.
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// is the standard comment sequence, but we prefer "C" since it inhibits m4
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macro expansion. See comments in ia64-defs.m4.
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REGISTER USAGE
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Special:
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r0: constant 0
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r1: global pointer (gp)
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r8: return value
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r12: stack pointer (sp)
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r13: thread pointer (tp)
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Caller-saves: r8-r11 r14-r31 f6-f15 f32-f127
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Caller-saves but rotating: r32-
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================================================================
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mpn_add_n, mpn_sub_n:
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The current code runs at 1.25 c/l on Itanium 2.
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================================================================
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mpn_mul_1:
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The current code runs at 2 c/l on Itanium 2.
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Using a blocked approach, working off of 4 separate places in the operands,
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one could make use of the xma accumulation, and approach 1 c/l.
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ldf8 [up]
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xma.l
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xma.hu
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stf8 [wrp]
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================================================================
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mpn_addmul_1:
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The current code runs at 2 c/l on Itanium 2.
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It seems possible to use a blocked approach, as with mpn_mul_1. We should
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read rp[] to integer registers, allowing for just one getf.sig per cycle.
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ld8 [rp]
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ldf8 [up]
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xma.l
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xma.hu
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getf.sig
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add+add+cmp+cmp
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st8 [wrp]
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These 10 instructions can be scheduled to approach 1.667 cycles, and with
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the 4 cycle latency of xma, this means we need at least 3 blocks. Using
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ldfp8 we could approach 1.583 c/l.
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================================================================
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mpn_submul_1:
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The current code runs at 2.25 c/l on Itanium 2. Getting to 2 c/l requires
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ldfp8 with all alignment headache that implies.
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================================================================
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mpn_addmul_N
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For best speed, we need to give up using mpn_addmul_2 as the main multiply
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building block, and instead take multiple v limbs per loop. For the Itanium
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1, we need to take about 8 limbs at a time for full speed. For the Itanium
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2, something like mpn_addmul_4 should be enough.
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The add+cmp+cmp+add we use on the other codes is optimal for shortening
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recurrencies (1 cycle) but the sequence takes up 4 execution slots. When
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recurrency depth is not critical, a more standard 3-cycle add+cmp+add is
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better.
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/* First load the 8 values from v */
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ldfp8 v0, v1 = [r35], 16;;
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ldfp8 v2, v3 = [r35], 16;;
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ldfp8 v4, v5 = [r35], 16;;
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ldfp8 v6, v7 = [r35], 16;;
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/* In the inner loop, get a new U limb and store a result limb. */
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mov lc = un
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Loop: ldf8 u0 = [r33], 8
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ld8 r0 = [r32]
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xma.l lp0 = v0, u0, hp0
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xma.hu hp0 = v0, u0, hp0
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xma.l lp1 = v1, u0, hp1
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xma.hu hp1 = v1, u0, hp1
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xma.l lp2 = v2, u0, hp2
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xma.hu hp2 = v2, u0, hp2
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xma.l lp3 = v3, u0, hp3
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xma.hu hp3 = v3, u0, hp3
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xma.l lp4 = v4, u0, hp4
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xma.hu hp4 = v4, u0, hp4
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xma.l lp5 = v5, u0, hp5
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xma.hu hp5 = v5, u0, hp5
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xma.l lp6 = v6, u0, hp6
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xma.hu hp6 = v6, u0, hp6
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xma.l lp7 = v7, u0, hp7
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xma.hu hp7 = v7, u0, hp7
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getf.sig l0 = lp0
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getf.sig l1 = lp1
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getf.sig l2 = lp2
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getf.sig l3 = lp3
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getf.sig l4 = lp4
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getf.sig l5 = lp5
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getf.sig l6 = lp6
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add+cmp+add xx, l0, r0
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add+cmp+add acc0, acc1, l1
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add+cmp+add acc1, acc2, l2
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add+cmp+add acc2, acc3, l3
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add+cmp+add acc3, acc4, l4
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add+cmp+add acc4, acc5, l5
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add+cmp+add acc5, acc6, l6
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getf.sig acc6 = lp7
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st8 [r32] = xx, 8
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br.cloop Loop
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49 insn at max 6 insn/cycle: 8.167 cycles/limb8
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11 memops at max 2 memops/cycle: 5.5 cycles/limb8
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16 fpops at max 2 fpops/cycle: 8 cycles/limb8
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21 intops at max 4 intops/cycle: 5.25 cycles/limb8
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11+21 memops+intops at max 4/cycle 8 cycles/limb8
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================================================================
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mpn_lshift, mpn_rshift
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The current code runs at 1 cycle/limb on Itanium 2.
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Using 63 separate loops, we could use the double-word shrp instruction.
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That instruction has a plain single-cycle latency. We need 63 loops since
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this instruction only accept immediate count. That would lead to a somewhat
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silly code size, but the speed would be 0.75 c/l on Itanium 2 (by using shrp
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each cycle plus shl/shr going down I1 for a further limb every second
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cycle).
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================================================================
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mpn_copyi, mpn_copyd
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The current code runs at 0.5 c/l on Itanium 2. But that is just for L1
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cache hit. The 4-way unrolled loop takes just 2 cycles, and thus load-use
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scheduling isn't great. It might be best to actually use modulo scheduled
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loops, since that will allow us to do better load-use scheduling without too
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much unrolling.
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Depending on size or operand alignment, we get 1 c/l or 0.5 c/l on Itanium
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2, according to tune/speed. Cache bank conflicts?
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REFERENCES
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Intel Itanium Architecture Software Developer's Manual, volumes 1 to 3,
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Intel document 245317-004, 245318-004, 245319-004 October 2002. Volume 1
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includes an Itanium optimization guide.
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Intel Itanium Processor-specific Application Binary Interface (ABI), Intel
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document 245370-003, May 2001. Describes C type sizes, dynamic linking,
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etc.
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Intel Itanium Architecture Assembly Language Reference Guide, Intel document
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248801-004, 2000-2002. Describes assembly instruction syntax and other
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directives.
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Itanium Software Conventions and Runtime Architecture Guide, Intel document
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245358-003, May 2001. Describes calling conventions, including stack
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unwinding requirements.
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Intel Itanium Processor Reference Manual for Software Optimization, Intel
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document 245473-003, November 2001.
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Intel Itanium-2 Processor Reference Manual for Software Development and
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Optimization, Intel document 251110-003, May 2004.
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All the above documents can be found online at
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http://developer.intel.com/design/itanium/manuals.htm
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