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f133d007f9
Old version was from 2012-05-06, 6.1.2 is from 2016-12-16 A lot of support for newer processors and speedups since then See gmp/NEWS for details
159 lines
3.4 KiB
NASM
159 lines
3.4 KiB
NASM
dnl AMD64 mpn_divexact_1 -- mpn by limb exact division.
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dnl Copyright 2001, 2002, 2004-2006, 2011, 2012 Free Software Foundation, Inc.
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or modify
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dnl it under the terms of either:
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dnl
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dnl * the GNU Lesser General Public License as published by the Free
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dnl Software Foundation; either version 3 of the License, or (at your
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dnl option) any later version.
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dnl
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dnl or
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dnl
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dnl * the GNU General Public License as published by the Free Software
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dnl Foundation; either version 2 of the License, or (at your option) any
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dnl later version.
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dnl
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dnl or both in parallel, as here.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful, but
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dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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dnl for more details.
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dnl
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dnl You should have received copies of the GNU General Public License and the
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dnl GNU Lesser General Public License along with the GNU MP Library. If not,
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dnl see https://www.gnu.org/licenses/.
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include(`../config.m4')
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C cycles/limb
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C AMD K8,K9 10
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C AMD K10 10
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C Intel P4 33
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C Intel core2 13.25
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C Intel corei 14
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C Intel atom 42
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C VIA nano 43
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C A quick adoption of the 32-bit K7 code.
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C INPUT PARAMETERS
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C rp rdi
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C up rsi
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C n rdx
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C divisor rcx
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ABI_SUPPORT(DOS64)
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ABI_SUPPORT(STD64)
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ASM_START()
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TEXT
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ALIGN(16)
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PROLOGUE(mpn_divexact_1)
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FUNC_ENTRY(4)
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push %rbx
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mov %rcx, %rax
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xor R32(%rcx), R32(%rcx) C shift count
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mov %rdx, %r8
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bt $0, R32(%rax)
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jnc L(evn) C skip bsfq unless divisor is even
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L(odd): mov %rax, %rbx
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shr R32(%rax)
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and $127, R32(%rax) C d/2, 7 bits
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LEA( binvert_limb_table, %rdx)
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movzbl (%rdx,%rax), R32(%rax) C inv 8 bits
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mov %rbx, %r11 C d without twos
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lea (%rax,%rax), R32(%rdx) C 2*inv
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imul R32(%rax), R32(%rax) C inv*inv
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imul R32(%rbx), R32(%rax) C inv*inv*d
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sub R32(%rax), R32(%rdx) C inv = 2*inv - inv*inv*d, 16 bits
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lea (%rdx,%rdx), R32(%rax) C 2*inv
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imul R32(%rdx), R32(%rdx) C inv*inv
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imul R32(%rbx), R32(%rdx) C inv*inv*d
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sub R32(%rdx), R32(%rax) C inv = 2*inv - inv*inv*d, 32 bits
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lea (%rax,%rax), %r10 C 2*inv
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imul %rax, %rax C inv*inv
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imul %rbx, %rax C inv*inv*d
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sub %rax, %r10 C inv = 2*inv - inv*inv*d, 64 bits
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lea (%rsi,%r8,8), %rsi C up end
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lea -8(%rdi,%r8,8), %rdi C rp end
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neg %r8 C -n
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mov (%rsi,%r8,8), %rax C up[0]
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inc %r8
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jz L(one)
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mov (%rsi,%r8,8), %rdx C up[1]
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shrd R8(%rcx), %rdx, %rax
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xor R32(%rbx), R32(%rbx)
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jmp L(ent)
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L(evn): bsf %rax, %rcx
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shr R8(%rcx), %rax
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jmp L(odd)
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ALIGN(8)
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L(top):
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C rax q
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C rbx carry bit, 0 or 1
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C rcx shift
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C rdx
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C rsi up end
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C rdi rp end
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C r8 counter, limbs, negative
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C r10 d^(-1) mod 2^64
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C r11 d, shifted down
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mul %r11 C carry limb in rdx 0 10
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mov -8(%rsi,%r8,8), %rax C
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mov (%rsi,%r8,8), %r9 C
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shrd R8(%rcx), %r9, %rax C
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nop C
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sub %rbx, %rax C apply carry bit
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setc %bl C
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sub %rdx, %rax C apply carry limb 5
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adc $0, %rbx C 6
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L(ent): imul %r10, %rax C 6
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mov %rax, (%rdi,%r8,8) C
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inc %r8 C
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jnz L(top)
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mul %r11 C carry limb in rdx
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mov -8(%rsi), %rax C up high limb
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shr R8(%rcx), %rax
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sub %rbx, %rax C apply carry bit
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sub %rdx, %rax C apply carry limb
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imul %r10, %rax
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mov %rax, (%rdi)
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pop %rbx
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FUNC_EXIT()
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ret
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L(one): shr R8(%rcx), %rax
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imul %r10, %rax
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mov %rax, (%rdi)
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pop %rbx
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FUNC_EXIT()
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ret
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EPILOGUE()
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