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f133d007f9
Old version was from 2012-05-06, 6.1.2 is from 2016-12-16 A lot of support for newer processors and speedups since then See gmp/NEWS for details
168 lines
4.0 KiB
NASM
168 lines
4.0 KiB
NASM
dnl ARM mpn_addlsh1_n and mpn_sublsh1_n
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dnl Contributed to the GNU project by Torbjörn Granlund.
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dnl Copyright 2012 Free Software Foundation, Inc.
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or modify
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dnl it under the terms of either:
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dnl
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dnl * the GNU Lesser General Public License as published by the Free
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dnl Software Foundation; either version 3 of the License, or (at your
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dnl option) any later version.
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dnl
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dnl or
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dnl
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dnl * the GNU General Public License as published by the Free Software
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dnl Foundation; either version 2 of the License, or (at your option) any
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dnl later version.
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dnl
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dnl or both in parallel, as here.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful, but
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dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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dnl for more details.
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dnl
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dnl You should have received copies of the GNU General Public License and the
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dnl GNU Lesser General Public License along with the GNU MP Library. If not,
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dnl see https://www.gnu.org/licenses/.
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include(`../config.m4')
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C addlsh1_n sublsh1_n
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C cycles/limb cycles/limb
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C StrongARM ? ?
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C XScale ? ?
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C Cortex-A7 ? ?
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C Cortex-A8 ? ?
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C Cortex-A9 3.12 3.7
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C Cortex-A15 ? ?
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C TODO
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C * The addlsh1_n code runs well, but is only barely faster than mpn_addmul_1.
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C The sublsh1_n code could surely be tweaked, its REVCY slows down things
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C very much. If two insns are really needed, it might help to separate them
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C for better micro-parallelism.
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define(`rp', `r0')
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define(`up', `r1')
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define(`vp', `r2')
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define(`n', `r3')
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ifdef(`OPERATION_addlsh1_n', `
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define(`ADDSUB', adds)
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define(`ADDSUBC', adcs)
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define(`SETCY', `cmp $1, #1')
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define(`RETVAL', `adc r0, $1, #2')
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define(`SAVECY', `sbc $1, $2, #0')
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define(`RESTCY', `cmn $1, #1')
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define(`REVCY', `')
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define(`INICYR', `mov $1, #0')
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define(`r10r11', `r11')
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define(`func', mpn_addlsh1_n)
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define(`func_nc', mpn_addlsh1_nc)')
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ifdef(`OPERATION_sublsh1_n', `
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define(`ADDSUB', subs)
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define(`ADDSUBC', sbcs)
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define(`SETCY', `rsbs $1, $1, #0')
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define(`RETVAL', `adc r0, $1, #1')
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define(`SAVECY', `sbc $1, $1, $1')
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define(`RESTCY', `cmn $1, #1')
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define(`REVCY', `sbc $1, $1, $1
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cmn $1, #1')
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define(`INICYR', `mvn $1, #0')
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define(`r10r11', `r10')
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define(`func', mpn_sublsh1_n)
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define(`func_nc', mpn_sublsh1_nc)')
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MULFUNC_PROLOGUE(mpn_addlsh1_n mpn_sublsh1_n)
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ASM_START()
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PROLOGUE(func)
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push {r4-r10r11, r14}
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ifdef(`OPERATION_addlsh1_n', `
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mvn r11, #0
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')
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INICYR( r14)
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subs n, n, #3
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blt L(le2) C carry clear on branch path
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cmn r0, #0 C clear carry
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ldmia vp!, {r8, r9, r10}
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b L(mid)
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L(top): RESTCY( r14)
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ADDSUBC r4, r4, r8
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ADDSUBC r5, r5, r9
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ADDSUBC r6, r6, r10
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ldmia vp!, {r8, r9, r10}
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stmia rp!, {r4, r5, r6}
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REVCY(r14)
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adcs r8, r8, r8
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adcs r9, r9, r9
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adcs r10, r10, r10
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ldmia up!, {r4, r5, r6}
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SAVECY( r14, r11)
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subs n, n, #3
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blt L(exi)
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RESTCY( r12)
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ADDSUBC r4, r4, r8
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ADDSUBC r5, r5, r9
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ADDSUBC r6, r6, r10
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ldmia vp!, {r8, r9, r10}
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stmia rp!, {r4, r5, r6}
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REVCY(r12)
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L(mid): adcs r8, r8, r8
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adcs r9, r9, r9
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adcs r10, r10, r10
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ldmia up!, {r4, r5, r6}
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SAVECY( r12, r11)
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subs n, n, #3
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bge L(top)
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mov r7, r12 C swap alternating...
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mov r12, r14 C ...carry-save...
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mov r14, r7 C ...registers
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L(exi): RESTCY( r12)
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ADDSUBC r4, r4, r8
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ADDSUBC r5, r5, r9
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ADDSUBC r6, r6, r10
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stmia rp!, {r4, r5, r6}
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REVCY(r12)
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L(le2): tst n, #1 C n = {-1,-2,-3} map to [2], [1], [0]
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beq L(e1)
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L(e02): tst n, #2
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beq L(rt0)
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ldm vp, {r8, r9}
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adcs r8, r8, r8
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adcs r9, r9, r9
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ldm up, {r4, r5}
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SAVECY( r12, r11)
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RESTCY( r14)
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ADDSUBC r4, r4, r8
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ADDSUBC r5, r5, r9
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stm rp, {r4, r5}
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b L(rt1)
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L(e1): ldr r8, [vp]
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adcs r8, r8, r8
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ldr r4, [up]
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SAVECY( r12, r11)
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RESTCY( r14)
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ADDSUBC r4, r4, r8
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str r4, [rp]
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L(rt1): mov r14, r12
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REVCY(r12)
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L(rt0): RETVAL( r14)
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pop {r4-r10r11, r14}
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ret r14
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EPILOGUE()
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