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f133d007f9
Old version was from 2012-05-06, 6.1.2 is from 2016-12-16 A lot of support for newer processors and speedups since then See gmp/NEWS for details
168 lines
3.6 KiB
NASM
168 lines
3.6 KiB
NASM
dnl Alpha mpn_addlsh2_n/mpn_sublsh2_n -- rp[] = up[] +- (vp[] << 2).
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dnl Copyright 2003, 2013 Free Software Foundation, Inc.
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or modify
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dnl it under the terms of either:
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dnl
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dnl * the GNU Lesser General Public License as published by the Free
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dnl Software Foundation; either version 3 of the License, or (at your
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dnl option) any later version.
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dnl
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dnl or
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dnl
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dnl * the GNU General Public License as published by the Free Software
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dnl Foundation; either version 2 of the License, or (at your option) any
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dnl later version.
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dnl
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dnl or both in parallel, as here.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful, but
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dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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dnl for more details.
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dnl
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dnl You should have received copies of the GNU General Public License and the
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dnl GNU Lesser General Public License along with the GNU MP Library. If not,
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dnl see https://www.gnu.org/licenses/.
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include(`../config.m4')
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C cycles/limb
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C EV4: ?
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C EV5: 6
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C EV6: 3.75
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C TODO
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C * Tune to reach 3.5 c/l on ev6 and 5.75 c/l on ev5.
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define(`rp',`r16')
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define(`up',`r17')
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define(`vp',`r18')
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define(`n', `r19')
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define(`u0', `r8')
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define(`u1', `r1')
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define(`v0', `r4')
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define(`v1', `r5')
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define(`cy0', `r0')
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define(`cy1', `r20')
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define(`cy', `r22')
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define(`rr', `r24')
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define(`ps', `r25')
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define(`sl', `r28')
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ifdef(`OPERATION_addlsh2_n',`
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define(ADDSUB, addq)
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define(CARRY, `cmpult $1,$2,$3')
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define(func, mpn_addlsh2_n)
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')
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ifdef(`OPERATION_sublsh2_n',`
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define(ADDSUB, subq)
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define(CARRY, `cmpult $2,$1,$3')
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define(func, mpn_sublsh2_n)
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')
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MULFUNC_PROLOGUE(mpn_addlsh2_n mpn_sublsh2_n)
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ASM_START()
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PROLOGUE(func)
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and n, 2, cy0
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blbs n, L(bx1)
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L(bx0): ldq v1, 0(vp)
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ldq u1, 0(up)
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bis r31, r31, r2
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bne cy0, L(b10)
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L(b00): lda vp, 48(vp)
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lda up, -16(up)
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lda rp, -8(rp)
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s4addq v1, r31, sl
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br r31, L(lo0)
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L(b10): lda vp, 32(vp)
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lda rp, 8(rp)
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lda cy0, 0(r31)
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br r31, L(lo2)
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L(bx1): ldq v0, 0(vp)
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ldq u0, 0(up)
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lda cy1, 0(r31)
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bis r31, r31, r3
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nop
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beq cy0, L(b01)
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L(b11): lda vp, 40(vp)
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lda up, -24(up)
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lda rp, 16(rp)
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br r31, L(lo3)
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L(b01): lda n, -4(n)
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ble n, L(end)
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lda vp, 24(vp)
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lda up, -8(up)
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ALIGN(16)
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L(top): s4addq v0, r3, sl C combined vlimb
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ldq v1, -16(vp)
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ADDSUB u0, sl, ps C ulimb + (vlimb << 1)
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ldq u1, 16(up)
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srl v0, 62, r2 C high v bits
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ADDSUB ps, cy1, rr C consume carry from previous operation
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CARRY( ps, u0, cy0) C carry out #2
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stq rr, 0(rp)
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CARRY( rr, ps, cy) C carry out #3
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lda vp, 32(vp) C bookkeeping
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addq cy, cy0, cy0 C final carry out
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s4addq v1, r2, sl
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L(lo0): ldq v0, -40(vp)
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ADDSUB u1, sl, ps
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ldq u0, 24(up)
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srl v1, 62, r3
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ADDSUB ps, cy0, rr
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CARRY( ps, u1, cy1)
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stq rr, 8(rp)
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CARRY( rr, ps, cy)
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lda rp, 32(rp) C bookkeeping
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addq cy, cy1, cy1
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L(lo3): s4addq v0, r3, sl
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ldq v1, -32(vp)
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ADDSUB u0, sl, ps
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ldq u1, 32(up)
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srl v0, 62, r2
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ADDSUB ps, cy1, rr
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CARRY( ps, u0, cy0)
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stq rr, -16(rp)
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CARRY( rr, ps, cy)
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lda up, 32(up) C bookkeeping
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addq cy, cy0, cy0
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L(lo2): s4addq v1, r2, sl
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ldq v0, -24(vp)
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ADDSUB u1, sl, ps
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ldq u0, 8(up)
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srl v1, 62, r3
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ADDSUB ps, cy0, rr
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CARRY( ps, u1, cy1)
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stq rr, -8(rp)
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CARRY( rr, ps, cy)
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lda n, -4(n) C bookkeeping
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addq cy, cy1, cy1
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bgt n, L(top)
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L(end): s4addq v0, r3, sl
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ADDSUB u0, sl, ps
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srl v0, 62, r2
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ADDSUB ps, cy1, rr
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CARRY( ps, u0, cy0)
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stq rr, 0(rp)
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CARRY( rr, ps, cy)
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addq cy, cy0, cy0
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addq cy0, r2, r0
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ret r31,(r26),1
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EPILOGUE()
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ASM_END()
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