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f133d007f9
Old version was from 2012-05-06, 6.1.2 is from 2016-12-16 A lot of support for newer processors and speedups since then See gmp/NEWS for details
211 lines
4.3 KiB
NASM
211 lines
4.3 KiB
NASM
dnl PowerPC-64 mpn_lshiftc -- rp[] = ~up[] << cnt
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dnl Copyright 2003, 2005, 2010 Free Software Foundation, Inc.
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or modify
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dnl it under the terms of either:
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dnl
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dnl * the GNU Lesser General Public License as published by the Free
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dnl Software Foundation; either version 3 of the License, or (at your
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dnl option) any later version.
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dnl
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dnl or
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dnl
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dnl * the GNU General Public License as published by the Free Software
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dnl Foundation; either version 2 of the License, or (at your option) any
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dnl later version.
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dnl
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dnl or both in parallel, as here.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful, but
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dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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dnl for more details.
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dnl
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dnl You should have received copies of the GNU General Public License and the
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dnl GNU Lesser General Public License along with the GNU MP Library. If not,
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dnl see https://www.gnu.org/licenses/.
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include(`../config.m4')
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C cycles/limb
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C POWER3/PPC630 ?
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C POWER4/PPC970 ?
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C POWER5 2.25
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C POWER6 9.5
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C POWER7 2.15
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C TODO
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C * Try to reduce the number of needed live registers
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C * Micro-optimise header code
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C * Keep in synch with lshift.asm and rshift.asm
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C * Could the long-scheduled std insns be less scheduled?
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C INPUT PARAMETERS
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define(`rp', `r3')
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define(`up', `r4')
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define(`n', `r5')
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define(`cnt', `r6')
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define(`tnc',`r0')
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define(`u0',`r30')
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define(`u1',`r31')
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define(`retval',`r5')
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ASM_START()
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PROLOGUE(mpn_lshiftc)
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std r31, -8(r1)
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std r30, -16(r1)
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subfic tnc, cnt, 64
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sldi r7, n, 3 C byte count corresponding to n
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add up, up, r7 C up = up + n
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add rp, rp, r7 C rp = rp + n
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rldicl. r30, n, 0,62 C r30 = n & 3, set cr0
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cmpdi cr6, r30, 2
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addi r31, n, 3 C compute count...
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ld r10, -8(up) C load 1st limb for b00...b11
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srd retval, r10, tnc
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srdi r31, r31, 2 C ...for ctr
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mtctr r31 C copy count into ctr
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beq cr0, L(b00)
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blt cr6, L(b01)
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ld r11, -16(up) C load 2nd limb for b10 and b11
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beq cr6, L(b10)
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ALIGN(16)
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L(b11): sld r8, r10, cnt
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srd r9, r11, tnc
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ld u1, -24(up)
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addi up, up, -24
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sld r12, r11, cnt
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srd r7, u1, tnc
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addi rp, rp, 16
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bdnz L(gt3)
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nor r11, r8, r9
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sld r8, u1, cnt
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nor r8, r8, r8
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b L(cj3)
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ALIGN(16)
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L(gt3): ld u0, -8(up)
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nor r11, r8, r9
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sld r8, u1, cnt
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srd r9, u0, tnc
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ld u1, -16(up)
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nor r10, r12, r7
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b L(L11)
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ALIGN(32)
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L(b10): sld r12, r10, cnt
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addi rp, rp, 24
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srd r7, r11, tnc
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bdnz L(gt2)
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sld r8, r11, cnt
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nor r10, r12, r7
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nor r8, r8, r8
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b L(cj2)
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L(gt2): ld u0, -24(up)
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sld r8, r11, cnt
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srd r9, u0, tnc
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ld u1, -32(up)
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nor r10, r12, r7
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sld r12, u0, cnt
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srd r7, u1, tnc
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ld u0, -40(up)
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nor r11, r8, r9
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addi up, up, -16
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b L(L10)
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ALIGN(16)
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L(b00): ld u1, -16(up)
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sld r12, r10, cnt
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srd r7, u1, tnc
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ld u0, -24(up)
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sld r8, u1, cnt
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srd r9, u0, tnc
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ld u1, -32(up)
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nor r10, r12, r7
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sld r12, u0, cnt
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srd r7, u1, tnc
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addi rp, rp, 8
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bdz L(cj4)
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L(gt4): addi up, up, -32
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ld u0, -8(up)
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nor r11, r8, r9
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b L(L00)
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ALIGN(16)
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L(b01): bdnz L(gt1)
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sld r8, r10, cnt
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nor r8, r8, r8
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std r8, -8(rp)
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b L(ret)
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L(gt1): ld u0, -16(up)
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sld r8, r10, cnt
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srd r9, u0, tnc
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ld u1, -24(up)
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sld r12, u0, cnt
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srd r7, u1, tnc
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ld u0, -32(up)
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nor r11, r8, r9
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sld r8, u1, cnt
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srd r9, u0, tnc
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ld u1, -40(up)
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addi up, up, -40
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nor r10, r12, r7
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bdz L(end)
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ALIGN(32)
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L(top): sld r12, u0, cnt
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srd r7, u1, tnc
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ld u0, -8(up)
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std r11, -8(rp)
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nor r11, r8, r9
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L(L00): sld r8, u1, cnt
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srd r9, u0, tnc
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ld u1, -16(up)
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std r10, -16(rp)
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nor r10, r12, r7
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L(L11): sld r12, u0, cnt
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srd r7, u1, tnc
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ld u0, -24(up)
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std r11, -24(rp)
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nor r11, r8, r9
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L(L10): sld r8, u1, cnt
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srd r9, u0, tnc
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ld u1, -32(up)
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addi up, up, -32
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std r10, -32(rp)
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addi rp, rp, -32
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nor r10, r12, r7
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bdnz L(top)
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ALIGN(32)
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L(end): sld r12, u0, cnt
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srd r7, u1, tnc
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std r11, -8(rp)
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L(cj4): nor r11, r8, r9
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sld r8, u1, cnt
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std r10, -16(rp)
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nor r8, r8, r8
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L(cj3): nor r10, r12, r7
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std r11, -24(rp)
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L(cj2): std r10, -32(rp)
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std r8, -40(rp)
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L(ret): ld r31, -8(r1)
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ld r30, -16(r1)
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ifdef(`HAVE_ABI_mode32',
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` srdi r3, retval, 32
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mr r4, retval
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',` mr r3, retval')
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blr
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EPILOGUE()
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