diff --git a/headers/private/graphics/radeon_hd/avivo.h b/headers/private/graphics/radeon_hd/avivo.h new file mode 100644 index 0000000000..bd4dab793b --- /dev/null +++ b/headers/private/graphics/radeon_hd/avivo.h @@ -0,0 +1,65 @@ +/* + * Copyright 2009 Advanced Micro Devices, Inc. + * Copyright 2009 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef AVIVO_H +#define AVIVO_H + + +#define D1CRTC_CONTROL 0x6080 +#define CRTC_EN (1 << 0) +#define D1CRTC_STATUS 0x609c +#define D1CRTC_UPDATE_LOCK 0x60E8 +#define D1GRPH_SWAP_CNTL 0x610C +#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 +#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 + +#define D2CRTC_CONTROL 0x6880 +#define D2CRTC_STATUS 0x689c +#define D2CRTC_UPDATE_LOCK 0x68E8 +#define D2GRPH_SWAP_CNTL 0x690C +#define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 +#define D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 + +#define D1VGA_CONTROL 0x0330 +#define DVGA_CONTROL_MODE_ENABLE (1 << 0) +#define DVGA_CONTROL_TIMING_SELECT (1 << 8) +#define DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9) +#define DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10) +#define DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16) +#define DVGA_CONTROL_ROTATE (1 << 24) +#define D2VGA_CONTROL 0x0338 + +#define VGA_HDP_CONTROL 0x328 +#define VGA_MEM_PAGE_SELECT_EN (1 << 0) +#define VGA_MEMORY_DISABLE (1 << 4) +#define VGA_RBBM_LOCK_DISABLE (1 << 8) +#define VGA_SOFT_RESET (1 << 16) +#define VGA_MEMORY_BASE_ADDRESS 0x0310 +#define VGA_RENDER_CONTROL 0x0300 +#define VGA_VSTATUS_CNTL_MASK 0x00030000 + + +#endif diff --git a/headers/private/graphics/radeon_hd/r500_reg.h b/headers/private/graphics/radeon_hd/r500_reg.h index fc43705991..93afeea84b 100644 --- a/headers/private/graphics/radeon_hd/r500_reg.h +++ b/headers/private/graphics/radeon_hd/r500_reg.h @@ -398,11 +398,7 @@ */ #define AVIVO_D1GRPH_LUT_SEL 0x6108 #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 -#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 -#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 -#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c -#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c #define AVIVO_D1GRPH_PITCH 0x6120 #define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 #define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 diff --git a/headers/private/graphics/radeon_hd/r600_reg.h b/headers/private/graphics/radeon_hd/r600_reg.h index 215c2a1de2..73e50db477 100644 --- a/headers/private/graphics/radeon_hd/r600_reg.h +++ b/headers/private/graphics/radeon_hd/r600_reg.h @@ -29,6 +29,10 @@ #define __R600_REG_H__ +#define R600_CRTC0_REGISTER_OFFSET 0x0 +#define R600_CRTC1_REGISTER_OFFSET 0x800 + + #define R600_PCIE_PORT_INDEX 0x0038 #define R600_PCIE_PORT_DATA 0x003c @@ -50,29 +54,10 @@ #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 -#define R700_MC_VM_FB_LOCATION 0x2024 -#define R700_MC_FB_BASE_MASK 0x0000FFFF -#define R700_MC_FB_BASE_SHIFT 0 -#define R700_MC_FB_TOP_MASK 0xFFFF0000 -#define R700_MC_FB_TOP_SHIFT 16 -#define R700_MC_VM_AGP_TOP 0x2028 -#define R700_MC_AGP_TOP_MASK 0x0003FFFF -#define R700_MC_AGP_TOP_SHIFT 0 -#define R700_MC_VM_AGP_BOT 0x202c -#define R700_MC_AGP_BOT_MASK 0x0003FFFF -#define R700_MC_AGP_BOT_SHIFT 0 -#define R700_MC_VM_AGP_BASE 0x2030 -#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 -#define R700_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF -#define R700_LOGICAL_PAGE_NUMBER_SHIFT 0 -#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 -#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c - #define R600_RAMCFG 0x2408 # define R600_CHANSIZE (1 << 7) # define R600_CHANSIZE_OVERRIDE (1 << 10) - #define R600_GENERAL_PWRMGT 0x618 # define R600_OPEN_DRAIN_PADS (1 << 11) diff --git a/headers/private/graphics/radeon_hd/r700_reg.h b/headers/private/graphics/radeon_hd/r700_reg.h new file mode 100644 index 0000000000..bf38804649 --- /dev/null +++ b/headers/private/graphics/radeon_hd/r700_reg.h @@ -0,0 +1,404 @@ +/* + * Copyright 2009 Advanced Micro Devices, Inc. + * Copyright 2009 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef RV770_H +#define RV770_H + + +#define R7XX_MAX_SH_GPRS 256 +#define R7XX_MAX_TEMP_GPRS 16 +#define R7XX_MAX_SH_THREADS 256 +#define R7XX_MAX_SH_STACK_ENTRIES 4096 +#define R7XX_MAX_BACKENDS 8 +#define R7XX_MAX_BACKENDS_MASK 0xff +#define R7XX_MAX_SIMDS 16 +#define R7XX_MAX_SIMDS_MASK 0xffff +#define R7XX_MAX_PIPES 8 +#define R7XX_MAX_PIPES_MASK 0xff + +#if 0 +/* Registers */ +#define CB_COLOR0_BASE 0x28040 +#define CB_COLOR1_BASE 0x28044 +#define CB_COLOR2_BASE 0x28048 +#define CB_COLOR3_BASE 0x2804C +#define CB_COLOR4_BASE 0x28050 +#define CB_COLOR5_BASE 0x28054 +#define CB_COLOR6_BASE 0x28058 +#define CB_COLOR7_BASE 0x2805C +#define CB_COLOR7_FRAG 0x280FC + +#define CC_GC_SHADER_PIPE_CONFIG 0x8950 +#define CC_RB_BACKEND_DISABLE 0x98F4 +#define BACKEND_DISABLE(x) ((x) << 16) +#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 + +#define CGTS_SYS_TCC_DISABLE 0x3F90 +#define CGTS_TCC_DISABLE 0x9148 +#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 +#define CGTS_USER_TCC_DISABLE 0x914C + +#define CP_ME_CNTL 0x86D8 +#define CP_ME_HALT (1<<28) +#define CP_PFP_HALT (1<<26) +#define CP_ME_RAM_DATA 0xC160 +#define CP_ME_RAM_RADDR 0xC158 +#define CP_ME_RAM_WADDR 0xC15C +#define CP_MEQ_THRESHOLDS 0x8764 +#define STQ_SPLIT(x) ((x) << 0) +#define CP_PERFMON_CNTL 0x87FC +#define CP_PFP_UCODE_ADDR 0xC150 +#define CP_PFP_UCODE_DATA 0xC154 +#define CP_QUEUE_THRESHOLDS 0x8760 +#define ROQ_IB1_START(x) ((x) << 0) +#define ROQ_IB2_START(x) ((x) << 8) +#define CP_RB_CNTL 0xC104 +#define RB_BUFSZ(x) ((x) << 0) +#define RB_BLKSZ(x) ((x) << 8) +#define RB_NO_UPDATE (1 << 27) +#define RB_RPTR_WR_ENA (1 << 31) +#define BUF_SWAP_32BIT (2 << 16) +#define CP_RB_RPTR 0x8700 +#define CP_RB_RPTR_ADDR 0xC10C +#define CP_RB_RPTR_ADDR_HI 0xC110 +#define CP_RB_RPTR_WR 0xC108 +#define CP_RB_WPTR 0xC114 +#define CP_RB_WPTR_ADDR 0xC118 +#define CP_RB_WPTR_ADDR_HI 0xC11C +#define CP_RB_WPTR_DELAY 0x8704 +#define CP_SEM_WAIT_TIMER 0x85BC + +#define DB_DEBUG3 0x98B0 +#define DB_CLK_OFF_DELAY(x) ((x) << 11) +#define DB_DEBUG4 0x9B8C +#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) + +#define DCP_TILING_CONFIG 0x6CA0 +#define PIPE_TILING(x) ((x) << 1) +#define BANK_TILING(x) ((x) << 4) +#define GROUP_SIZE(x) ((x) << 6) +#define ROW_TILING(x) ((x) << 8) +#define BANK_SWAPS(x) ((x) << 11) +#define SAMPLE_SPLIT(x) ((x) << 14) +#define BACKEND_MAP(x) ((x) << 16) + +#define GB_TILING_CONFIG 0x98F0 + +#define GC_USER_SHADER_PIPE_CONFIG 0x8954 +#define INACTIVE_QD_PIPES(x) ((x) << 8) +#define INACTIVE_QD_PIPES_MASK 0x0000FF00 +#define INACTIVE_SIMDS(x) ((x) << 16) +#define INACTIVE_SIMDS_MASK 0x00FF0000 + +#define GRBM_CNTL 0x8000 +#define GRBM_READ_TIMEOUT(x) ((x) << 0) +#define GRBM_SOFT_RESET 0x8020 +#define SOFT_RESET_CP (1<<0) +#define GRBM_STATUS 0x8010 +#define CMDFIFO_AVAIL_MASK 0x0000000F +#define GUI_ACTIVE (1<<31) +#define GRBM_STATUS2 0x8014 + +#define CG_MULT_THERMAL_STATUS 0x740 +#define ASIC_T(x) ((x) << 16) +#define ASIC_T_MASK 0x3FF0000 +#define ASIC_T_SHIFT 16 +#endif + +#define HDP_HOST_PATH_CNTL 0x2C00 +#define HDP_NONSURFACE_BASE 0x2C04 +#define HDP_NONSURFACE_INFO 0x2C08 +#define HDP_NONSURFACE_SIZE 0x2C0C +#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 +#define HDP_TILING_CONFIG 0x2F3C +#define HDP_DEBUG1 0x2F34 + +#define R700_MC_SHARED_CHMAP 0x2004 +#define NOOFCHAN_SHIFT 12 +#define NOOFCHAN_MASK 0x00003000 +#define R700_MC_SHARED_CHREMAP 0x2008 + +#define R700_MC_ARB_RAMCFG 0x2760 +#define NOOFBANK_SHIFT 0 +#define NOOFBANK_MASK 0x00000003 +#define NOOFRANK_SHIFT 2 +#define NOOFRANK_MASK 0x00000004 +#define NOOFROWS_SHIFT 3 +#define NOOFROWS_MASK 0x00000038 +#define NOOFCOLS_SHIFT 6 +#define NOOFCOLS_MASK 0x000000C0 +#define CHANSIZE_SHIFT 8 +#define CHANSIZE_MASK 0x00000100 +#define BURSTLENGTH_SHIFT 9 +#define BURSTLENGTH_MASK 0x00000200 +#define CHANSIZE_OVERRIDE (1 << 11) +#define R700_MC_VM_AGP_TOP 0x2028 +#define R700_MC_VM_AGP_BOT 0x202C +#define R700_MC_VM_AGP_BASE 0x2030 +#define R700_MC_VM_FB_LOCATION 0x2024 +#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 +#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 +#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223C +#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 +#define ENABLE_L1_TLB (1 << 0) +#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) +#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) +#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) +#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) +#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) +#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) +#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) +#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) +#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 +#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 +#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265C +#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C +#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 +#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 + +#define PA_CL_ENHANCE 0x8A14 +#define CLIP_VTX_REORDER_ENA (1 << 0) +#define NUM_CLIP_SEQ(x) ((x) << 1) +#define PA_SC_AA_CONFIG 0x28C04 +#define PA_SC_CLIPRECT_RULE 0x2820C +#define PA_SC_EDGERULE 0x28230 +#define PA_SC_FIFO_SIZE 0x8BCC +#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) +#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) +#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 +#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) +#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) +#define PA_SC_LINE_STIPPLE 0x28A0C +#define PA_SC_LINE_STIPPLE_STATE 0x8B10 +#define PA_SC_MODE_CNTL 0x28A4C +#define PA_SC_MULTI_CHIP_CNTL 0x8B20 +#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) + +#define R700_SCRATCH_REG0 0x8500 +#define R700_SCRATCH_REG1 0x8504 +#define R700_SCRATCH_REG2 0x8508 +#define R700_SCRATCH_REG3 0x850C +#define R700_SCRATCH_REG4 0x8510 +#define R700_SCRATCH_REG5 0x8514 +#define R700_SCRATCH_REG6 0x8518 +#define R700_SCRATCH_REG7 0x851C +#define R700_SCRATCH_UMSK 0x8540 +#define R700_SCRATCH_ADDR 0x8544 + +#if 0 +#define SMX_DC_CTL0 0xA020 +#define USE_HASH_FUNCTION (1 << 0) +#define CACHE_DEPTH(x) ((x) << 1) +#define FLUSH_ALL_ON_EVENT (1 << 10) +#define STALL_ON_EVENT (1 << 11) +#define SMX_EVENT_CTL 0xA02C +#define ES_FLUSH_CTL(x) ((x) << 0) +#define GS_FLUSH_CTL(x) ((x) << 3) +#define ACK_FLUSH_CTL(x) ((x) << 6) +#define SYNC_FLUSH_CTL (1 << 8) + +#define SPI_CONFIG_CNTL 0x9100 +#define GPR_WRITE_PRIORITY(x) ((x) << 0) +#define DISABLE_INTERP_1 (1 << 5) +#define SPI_CONFIG_CNTL_1 0x913C +#define VTX_DONE_DELAY(x) ((x) << 0) +#define INTERP_ONE_PRIM_PER_ROW (1 << 4) +#define SPI_INPUT_Z 0x286D8 +#define SPI_PS_IN_CONTROL_0 0x286CC +#define NUM_INTERP(x) ((x)<<0) +#define POSITION_ENA (1<<8) +#define POSITION_CENTROID (1<<9) +#define POSITION_ADDR(x) ((x)<<10) +#define PARAM_GEN(x) ((x)<<15) +#define PARAM_GEN_ADDR(x) ((x)<<19) +#define BARYC_SAMPLE_CNTL(x) ((x)<<26) +#define PERSP_GRADIENT_ENA (1<<28) +#define LINEAR_GRADIENT_ENA (1<<29) +#define POSITION_SAMPLE (1<<30) +#define BARYC_AT_SAMPLE_ENA (1<<31) + +#define SQ_CONFIG 0x8C00 +#define VC_ENABLE (1 << 0) +#define EXPORT_SRC_C (1 << 1) +#define DX9_CONSTS (1 << 2) +#define ALU_INST_PREFER_VECTOR (1 << 3) +#define DX10_CLAMP (1 << 4) +#define CLAUSE_SEQ_PRIO(x) ((x) << 8) +#define PS_PRIO(x) ((x) << 24) +#define VS_PRIO(x) ((x) << 26) +#define GS_PRIO(x) ((x) << 28) +#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0 +#define SIMDA_RING0(x) ((x)<<0) +#define SIMDA_RING1(x) ((x)<<8) +#define SIMDB_RING0(x) ((x)<<16) +#define SIMDB_RING1(x) ((x)<<24) +#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4 +#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8 +#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC +#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0 +#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 +#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 +#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC +#define ES_PRIO(x) ((x) << 30) +#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 +#define NUM_PS_GPRS(x) ((x) << 0) +#define NUM_VS_GPRS(x) ((x) << 16) +#define DYN_GPR_ENABLE (1 << 27) +#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) +#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 +#define NUM_GS_GPRS(x) ((x) << 0) +#define NUM_ES_GPRS(x) ((x) << 16) +#define SQ_MS_FIFO_SIZES 0x8CF0 +#define CACHE_FIFO_SIZE(x) ((x) << 0) +#define FETCH_FIFO_HIWATER(x) ((x) << 8) +#define DONE_FIFO_HIWATER(x) ((x) << 16) +#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) +#define SQ_STACK_RESOURCE_MGMT_1 0x8C10 +#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) +#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) +#define SQ_STACK_RESOURCE_MGMT_2 0x8C14 +#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) +#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) +#define SQ_THREAD_RESOURCE_MGMT 0x8C0C +#define NUM_PS_THREADS(x) ((x) << 0) +#define NUM_VS_THREADS(x) ((x) << 8) +#define NUM_GS_THREADS(x) ((x) << 16) +#define NUM_ES_THREADS(x) ((x) << 24) + +#define SX_DEBUG_1 0x9058 +#define ENABLE_NEW_SMX_ADDRESS (1 << 16) +#define SX_EXPORT_BUFFER_SIZES 0x900C +#define COLOR_BUFFER_SIZE(x) ((x) << 0) +#define POSITION_BUFFER_SIZE(x) ((x) << 8) +#define SMX_BUFFER_SIZE(x) ((x) << 16) +#define SX_MISC 0x28350 + +#define TA_CNTL_AUX 0x9508 +#define DISABLE_CUBE_WRAP (1 << 0) +#define DISABLE_CUBE_ANISO (1 << 1) +#define SYNC_GRADIENT (1 << 24) +#define SYNC_WALKER (1 << 25) +#define SYNC_ALIGNER (1 << 26) +#define BILINEAR_PRECISION_6_BIT (0 << 31) +#define BILINEAR_PRECISION_8_BIT (1 << 31) + +#define TCP_CNTL 0x9610 +#define TCP_CHAN_STEER 0x9614 + +#define VGT_CACHE_INVALIDATION 0x88C4 +#define CACHE_INVALIDATION(x) ((x)<<0) +#define VC_ONLY 0 +#define TC_ONLY 1 +#define VC_AND_TC 2 +#define AUTO_INVLD_EN(x) ((x) << 6) +#define NO_AUTO 0 +#define ES_AUTO 1 +#define GS_AUTO 2 +#define ES_AND_GS_AUTO 3 +#define VGT_ES_PER_GS 0x88CC +#define VGT_GS_PER_ES 0x88C8 +#define VGT_GS_PER_VS 0x88E8 +#define VGT_GS_VERTEX_REUSE 0x88D4 +#define VGT_NUM_INSTANCES 0x8974 +#define VGT_OUT_DEALLOC_CNTL 0x28C5C +#define DEALLOC_DIST_MASK 0x0000007F +#define VGT_STRMOUT_EN 0x28AB0 +#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 +#define VTX_REUSE_DEPTH_MASK 0x000000FF + +#define VM_CONTEXT0_CNTL 0x1410 +#define ENABLE_CONTEXT (1 << 0) +#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) +#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 +#define VM_L2_CNTL 0x1400 +#define ENABLE_L2_CACHE (1 << 0) +#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) +#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) +#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) +#define VM_L2_CNTL2 0x1404 +#define INVALIDATE_ALL_L1_TLBS (1 << 0) +#define INVALIDATE_L2_CACHE (1 << 1) +#define VM_L2_CNTL3 0x1408 +#define BANK_SELECT(x) ((x) << 0) +#define CACHE_UPDATE_MODE(x) ((x) << 6) +#define VM_L2_STATUS 0x140C +#define L2_BUSY (1 << 0) + +#define WAIT_UNTIL 0x8040 + +#define SRBM_STATUS 0x0E50 +#endif + +#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 +#define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 +#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 +#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 +#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c +#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c + +/* PCIE link stuff */ +#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ +#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ +# define LC_LINK_WIDTH_SHIFT 0 +# define LC_LINK_WIDTH_MASK 0x7 +# define LC_LINK_WIDTH_X0 0 +# define LC_LINK_WIDTH_X1 1 +# define LC_LINK_WIDTH_X2 2 +# define LC_LINK_WIDTH_X4 3 +# define LC_LINK_WIDTH_X8 4 +# define LC_LINK_WIDTH_X16 6 +# define LC_LINK_WIDTH_RD_SHIFT 4 +# define LC_LINK_WIDTH_RD_MASK 0x70 +# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) +# define LC_RECONFIG_NOW (1 << 8) +# define LC_RENEGOTIATION_SUPPORT (1 << 9) +# define LC_RENEGOTIATE_EN (1 << 10) +# define LC_SHORT_RECONFIG_EN (1 << 11) +# define LC_UPCONFIGURE_SUPPORT (1 << 12) +# define LC_UPCONFIGURE_DIS (1 << 13) +#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ +# define LC_GEN2_EN_STRAP (1 << 0) +# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) +# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) +# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) +# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) +# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 +# define LC_CURRENT_DATA_RATE (1 << 11) +# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) +# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) +# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) +# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) +#define MM_CFGREGS_CNTL 0x544c +# define MM_WR_TO_CFG_EN (1 << 3) +#define LINK_CNTL2 0x88 /* F0 */ +# define TARGET_LINK_SPEED_MASK (0xf << 0) +# define SELECTABLE_DEEMPHASIS (1 << 6) + +#endif diff --git a/headers/private/graphics/radeon_hd/radeon_hd.h b/headers/private/graphics/radeon_hd/radeon_hd.h index c17aa218b4..b0dde7300e 100644 --- a/headers/private/graphics/radeon_hd/radeon_hd.h +++ b/headers/private/graphics/radeon_hd/radeon_hd.h @@ -14,9 +14,10 @@ #include "radeon_reg.h" -#include "rhd_regs.h" // to phase out +#include "avivo.h" #include "r500_reg.h" #include "r600_reg.h" +#include "r700_reg.h" #include "r800_reg.h" #include @@ -168,41 +169,7 @@ struct radeon_free_graphics_memory { // registers #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> #define OLD_CONFIG_APER_SIZE 0x0108 // -#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c // r700> - -#define D2CRTC_CONTROL 0x6880 -#define D2CRTC_STATUS 0x689c -#define D2CRTC_UPDATE_LOCK 0x68E8 -#define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 -#define D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 -#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 // r700> -#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c // r700> - -#define D1VGA_CONTROL 0x0330 -#define DVGA_CONTROL_MODE_ENABLE (1 << 0) -#define DVGA_CONTROL_TIMING_SELECT (1 << 8) -#define DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9) -#define DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10) -#define DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16) -#define DVGA_CONTROL_ROTATE (1 << 24) -#define D2VGA_CONTROL 0x0338 - -#define VGA_HDP_CONTROL 0x328 -#define VGA_MEM_PAGE_SELECT_EN (1 << 0) -#define VGA_MEMORY_DISABLE (1 << 4) -#define VGA_RBBM_LOCK_DISABLE (1 << 8) -#define VGA_SOFT_RESET (1 << 16) -#define VGA_MEMORY_BASE_ADDRESS 0x0310 -#define VGA_RENDER_CONTROL 0x0300 -#define VGA_VSTATUS_CNTL_MASK 0x00030000 +#define CONFIG_MEMSIZE 0x5428 // r600> // PCI bridge memory management diff --git a/headers/private/graphics/radeon_hd/rhd_regs.h b/headers/private/graphics/radeon_hd/rhd_regs.h deleted file mode 100644 index 179a9d9419..0000000000 --- a/headers/private/graphics/radeon_hd/rhd_regs.h +++ /dev/null @@ -1,1160 +0,0 @@ -/* - * Copyright 2007, 2008 Luc Verhaegen - * Copyright 2007, 2008 Matthias Hopf - * Copyright 2007, 2008 Egbert Eich - * Copyright 2007, 2008 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _RHD_REGS_H -# define _RHD_REGS_H - -enum { - CLOCK_CNTL_INDEX = 0x8, /* (RW) */ - CLOCK_CNTL_DATA = 0xC, /* (RW) */ - BUS_CNTL = 0x4C, /* (RW) */ - MC_IND_INDEX = 0x70, /* (RW) */ - MC_IND_DATA = 0x74, /* (RW) */ - RS600_MC_INDEX = 0x70, - RS600_MC_DATA = 0x74, - RS690_MC_INDEX = 0x78, - RS690_MC_DATA = 0x7c, - RS780_MC_INDEX = 0x28f8, - RS780_MC_DATA = 0x28fc, - - RS60_MC_NB_MC_INDEX = 0x78, - RS60_MC_NB_MC_DATA = 0x7C, - CONFIG_CNTL = 0xE0, - PCIE_RS69_MC_INDEX = 0xE8, - PCIE_RS69_MC_DATA = 0xEC, - R5XX_CONFIG_MEMSIZE = 0x00F8, - - HDP_FB_LOCATION = 0x0134, - - SEPROM_CNTL1 = 0x1C0, /* (RW) */ - - AGP_BASE = 0x0170, - - GPIOPAD_MASK = 0x198, /* (RW) */ - GPIOPAD_A = 0x19C, /* (RW) */ - GPIOPAD_EN = 0x1A0, /* (RW) */ - VIPH_CONTROL = 0xC40, /* (RW) */ - - ROM_CNTL = 0x1600, - GENERAL_PWRMGT = 0x0618, - LOW_VID_LOWER_GPIO_CNTL = 0x0724, - MEDIUM_VID_LOWER_GPIO_CNTL = 0x0720, - HIGH_VID_LOWER_GPIO_CNTL = 0x071C, - CTXSW_VID_LOWER_GPIO_CNTL = 0x0718, - LOWER_GPIO_ENABLE = 0x0710, - - /* VGA registers */ - VGA_RENDER_CONTROL = 0x0300, - VGA_MODE_CONTROL = 0x0308, - VGA_MEMORY_BASE_ADDRESS = 0x0310, - VGA_HDP_CONTROL = 0x0328, - D1VGA_CONTROL = 0x0330, - D2VGA_CONTROL = 0x0338, - - EXT1_PPLL_REF_DIV_SRC = 0x0400, - EXT1_PPLL_REF_DIV = 0x0404, - EXT1_PPLL_UPDATE_LOCK = 0x0408, - EXT1_PPLL_UPDATE_CNTL = 0x040C, - EXT2_PPLL_REF_DIV_SRC = 0x0410, - EXT2_PPLL_REF_DIV = 0x0414, - EXT2_PPLL_UPDATE_LOCK = 0x0418, - EXT2_PPLL_UPDATE_CNTL = 0x041C, - - EXT1_PPLL_FB_DIV = 0x0430, - EXT2_PPLL_FB_DIV = 0x0434, - EXT1_PPLL_POST_DIV_SRC = 0x0438, - EXT1_PPLL_POST_DIV = 0x043C, - EXT2_PPLL_POST_DIV_SRC = 0x0440, - EXT2_PPLL_POST_DIV = 0x0444, - EXT1_PPLL_CNTL = 0x0448, - EXT2_PPLL_CNTL = 0x044C, - P1PLL_CNTL = 0x0450, - P2PLL_CNTL = 0x0454, - P1PLL_INT_SS_CNTL = 0x0458, - P2PLL_INT_SS_CNTL = 0x045C, - - P1PLL_DISP_CLK_CNTL = 0x0468, /* rv620+ */ - P2PLL_DISP_CLK_CNTL = 0x046C, /* rv620+ */ - EXT1_SYM_PPLL_POST_DIV = 0x0470, /* rv620+ */ - EXT2_SYM_PPLL_POST_DIV = 0x0474, /* rv620+ */ - - PCLK_CRTC1_CNTL = 0x0480, - PCLK_CRTC2_CNTL = 0x0484, - - /* these regs were reverse enginered, - * so the chance is high that the naming is wrong - * R6xx+ ??? */ - AUDIO_PLL1_MUL = 0x0514, - AUDIO_PLL1_DIV = 0x0518, - AUDIO_PLL2_MUL = 0x0524, - AUDIO_PLL2_DIV = 0x0528, - AUDIO_CLK_SRCSEL = 0x0534, - - DCCG_DISP_CLK_SRCSEL = 0x0538, /* rv620+ */ - - AGP_STATUS = 0x0F5C, - - R7XX_MC_VM_FB_LOCATION = 0x2024, - - R6XX_MC_VM_FB_LOCATION = 0x2180, - R6XX_HDP_NONSURFACE_BASE = 0x2C04, - R6XX_CONFIG_MEMSIZE = 0x5428, - R6XX_CONFIG_FB_BASE = 0x542C, /* AKA CONFIG_F0_BASE */ - /* PCI config space */ - PCI_CONFIG_SPACE_BASE = 0x5000, - PCI_CAPABILITIES_PTR = 0x5034, - - /* CRTC1 registers */ - D1CRTC_H_TOTAL = 0x6000, - D1CRTC_H_BLANK_START_END = 0x6004, - D1CRTC_H_SYNC_A = 0x6008, - D1CRTC_H_SYNC_A_CNTL = 0x600C, - D1CRTC_H_SYNC_B = 0x6010, - D1CRTC_H_SYNC_B_CNTL = 0x6014, - - D1CRTC_V_TOTAL = 0x6020, - D1CRTC_V_BLANK_START_END = 0x6024, - D1CRTC_V_SYNC_A = 0x6028, - D1CRTC_V_SYNC_A_CNTL = 0x602C, - D1CRTC_V_SYNC_B = 0x6030, - D1CRTC_V_SYNC_B_CNTL = 0x6034, - - D1CRTC_CONTROL = 0x6080, - D1CRTC_BLANK_CONTROL = 0x6084, - D1CRTC_INTERLACE_CONTROL = 0x6088, - D1CRTC_BLACK_COLOR = 0x6098, - D1CRTC_STATUS = 0x609C, - D1CRTC_COUNT_CONTROL = 0x60B4, - - /* D1GRPH registers */ - D1GRPH_ENABLE = 0x6100, - D1GRPH_CONTROL = 0x6104, - D1GRPH_LUT_SEL = 0x6108, - D1GRPH_SWAP_CNTL = 0x610C, - D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, - D1GRPH_SECONDARY_SURFACE_ADDRESS = 0x6118, - D1GRPH_PITCH = 0x6120, - D1GRPH_SURFACE_OFFSET_X = 0x6124, - D1GRPH_SURFACE_OFFSET_Y = 0x6128, - D1GRPH_X_START = 0x612C, - D1GRPH_Y_START = 0x6130, - D1GRPH_X_END = 0x6134, - D1GRPH_Y_END = 0x6138, - D1GRPH_UPDATE = 0x6144, - - /* LUT */ - DC_LUT_RW_SELECT = 0x6480, - DC_LUT_RW_MODE = 0x6484, - DC_LUT_RW_INDEX = 0x6488, - DC_LUT_SEQ_COLOR = 0x648C, - DC_LUT_PWL_DATA = 0x6490, - DC_LUT_30_COLOR = 0x6494, - DC_LUT_READ_PIPE_SELECT = 0x6498, - DC_LUT_WRITE_EN_MASK = 0x649C, - DC_LUT_AUTOFILL = 0x64A0, - - /* LUTA */ - DC_LUTA_CONTROL = 0x64C0, - DC_LUTA_BLACK_OFFSET_BLUE = 0x64C4, - DC_LUTA_BLACK_OFFSET_GREEN = 0x64C8, - DC_LUTA_BLACK_OFFSET_RED = 0x64CC, - DC_LUTA_WHITE_OFFSET_BLUE = 0x64D0, - DC_LUTA_WHITE_OFFSET_GREEN = 0x64D4, - DC_LUTA_WHITE_OFFSET_RED = 0x64D8, - - /* D1CUR */ - D1CUR_CONTROL = 0x6400, - D1CUR_SURFACE_ADDRESS = 0x6408, - D1CUR_SIZE = 0x6410, - D1CUR_POSITION = 0x6414, - D1CUR_HOT_SPOT = 0x6418, - D1CUR_UPDATE = 0x6424, - - /* D1MODE */ - D1MODE_DESKTOP_HEIGHT = 0x652C, - D1MODE_VLINE_START_END = 0x6538, - D1MODE_VLINE_STATUS = 0x653C, - D1MODE_VIEWPORT_START = 0x6580, - D1MODE_VIEWPORT_SIZE = 0x6584, - D1MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6588, - D1MODE_EXT_OVERSCAN_TOP_BOTTOM = 0x658C, - D1MODE_DATA_FORMAT = 0x6528, - - /* D1SCL */ - D1SCL_ENABLE = 0x6590, - D1SCL_TAP_CONTROL = 0x6594, - D1MODE_CENTER = 0x659C, /* guess */ - D1SCL_HVSCALE = 0x65A4, /* guess */ - D1SCL_HFILTER = 0x65B0, /* guess */ - D1SCL_VFILTER = 0x65C0, /* guess */ - D1SCL_UPDATE = 0x65CC, - D1SCL_DITHER = 0x65D4, /* guess */ - D1SCL_FLIP_CONTROL = 0x65D8, /* guess */ - - /* CRTC2 registers */ - D2CRTC_H_TOTAL = 0x6800, - D2CRTC_H_BLANK_START_END = 0x6804, - D2CRTC_H_SYNC_A = 0x6808, - D2CRTC_H_SYNC_A_CNTL = 0x680C, - D2CRTC_H_SYNC_B = 0x6810, - D2CRTC_H_SYNC_B_CNTL = 0x6814, - - D2CRTC_V_TOTAL = 0x6820, - D2CRTC_V_BLANK_START_END = 0x6824, - D2CRTC_V_SYNC_A = 0x6828, - D2CRTC_V_SYNC_A_CNTL = 0x682C, - D2CRTC_V_SYNC_B = 0x6830, - D2CRTC_V_SYNC_B_CNTL = 0x6834, - - D2CRTC_CONTROL = 0x6880, - D2CRTC_BLANK_CONTROL = 0x6884, - D2CRTC_BLACK_COLOR = 0x6898, - D2CRTC_INTERLACE_CONTROL = 0x6888, - D2CRTC_STATUS = 0x689C, - D2CRTC_COUNT_CONTROL = 0x68B4, - - /* D2GRPH registers */ - D2GRPH_ENABLE = 0x6900, - D2GRPH_CONTROL = 0x6904, - D2GRPH_LUT_SEL = 0x6908, - D2GRPH_SWAP_CNTL = 0x690C, - D2GRPH_PRIMARY_SURFACE_ADDRESS = 0x6910, - D2GRPH_SECONDARY_SURFACE_ADDRESS = 0x6918, - D2GRPH_PITCH = 0x6920, - D2GRPH_SURFACE_OFFSET_X = 0x6924, - D2GRPH_SURFACE_OFFSET_Y = 0x6928, - D2GRPH_X_START = 0x692C, - D2GRPH_Y_START = 0x6930, - D2GRPH_X_END = 0x6934, - D2GRPH_Y_END = 0x6938, - D2GRPH_UPDATE = 0x6944, - - /* LUTB */ - DC_LUTB_CONTROL = 0x6CC0, - DC_LUTB_BLACK_OFFSET_BLUE = 0x6CC4, - DC_LUTB_BLACK_OFFSET_GREEN = 0x6CC8, - DC_LUTB_BLACK_OFFSET_RED = 0x6CCC, - DC_LUTB_WHITE_OFFSET_BLUE = 0x6CD0, - DC_LUTB_WHITE_OFFSET_GREEN = 0x6CD4, - DC_LUTB_WHITE_OFFSET_RED = 0x6CD8, - - /* D2MODE */ - D2MODE_DESKTOP_HEIGHT = 0x6D2C, - D2MODE_VLINE_START_END = 0x6D38, - D2MODE_VLINE_STATUS = 0x6D3C, - D2MODE_VIEWPORT_START = 0x6D80, - D2MODE_VIEWPORT_SIZE = 0x6D84, - D2MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6D88, - D2MODE_EXT_OVERSCAN_TOP_BOTTOM = 0x6D8C, - D2MODE_DATA_FORMAT = 0x6D28, - - /* D2SCL */ - D2SCL_ENABLE = 0x6D90, - D2SCL_TAP_CONTROL = 0x6D94, - D2MODE_CENTER = 0x6D9C, /* guess */ - D2SCL_HVSCALE = 0x6DA4, /* guess */ - D2SCL_HFILTER = 0x6DB0, /* guess */ - D2SCL_VFILTER = 0x6DC0, /* guess */ - D2SCL_UPDATE = 0x6DCC, - D2SCL_DITHER = 0x6DD4, /* guess */ - D2SCL_FLIP_CONTROL = 0x6DD8, /* guess */ - - /* Audio, reverse enginered */ - AUDIO_ENABLE = 0x7300, /* RW */ - AUDIO_TIMING = 0x7344, /* RW */ - /* Audio params */ - AUDIO_VENDOR_ID = 0x7380, /* RW */ - AUDIO_REVISION_ID = 0x7384, /* RW */ - AUDIO_ROOT_NODE_COUNT = 0x7388, /* RW */ - AUDIO_NID1_NODE_COUNT = 0x738c, /* RW */ - AUDIO_NID1_TYPE = 0x7390, /* RW */ - AUDIO_SUPPORTED_SIZE_RATE = 0x7394, /* RW */ - AUDIO_SUPPORTED_CODEC = 0x7398, /* RW */ - AUDIO_SUPPORTED_POWER_STATES = 0x739c, /* RW */ - AUDIO_NID2_CAPS = 0x73a0, /* RW */ - AUDIO_NID3_CAPS = 0x73a4, /* RW */ - AUDIO_NID3_PIN_CAPS = 0x73a8, /* RW */ - /* Audio conn list */ - AUDIO_CONN_LIST_LEN = 0x73ac, /* RW */ - AUDIO_CONN_LIST = 0x73b0, /* RW */ - /* Audio verbs */ - AUDIO_RATE_BPS_CHANNEL = 0x73c0, /* RO */ - AUDIO_PLAYING = 0x73c4, /* RO */ - AUDIO_IMPLEMENTATION_ID = 0x73c8, /* RW */ - AUDIO_CONFIG_DEFAULT = 0x73cc, /* RW */ - AUDIO_PIN_SENSE = 0x73d0, /* RW */ - AUDIO_PIN_WIDGET_CNTL = 0x73d4, /* RO */ - AUDIO_STATUS_BITS = 0x73d8, /* RO */ - - R700_AUDIO_UNKNOWN = 0x7604, - - /* HDMI */ - HDMI_TMDS = 0x7400, - HDMI_LVTMA = 0x7700, - HDMI_DIG = 0x7800, - - /* R500 DAC A */ - DACA_ENABLE = 0x7800, - DACA_SOURCE_SELECT = 0x7804, - DACA_SYNC_TRISTATE_CONTROL = 0x7820, - DACA_SYNC_SELECT = 0x7824, - DACA_AUTODETECT_CONTROL = 0x7828, - DACA_AUTODETECT_INT_CONTROL = 0x7838, - DACA_FORCE_OUTPUT_CNTL = 0x783C, - DACA_FORCE_DATA = 0x7840, - DACA_POWERDOWN = 0x7850, - DACA_CONTROL1 = 0x7854, - DACA_CONTROL2 = 0x7858, - DACA_COMPARATOR_ENABLE = 0x785C, - DACA_COMPARATOR_OUTPUT = 0x7860, - -/* TMDSA */ - TMDSA_CNTL = 0x7880, - TMDSA_SOURCE_SELECT = 0x7884, - TMDSA_COLOR_FORMAT = 0x7888, - TMDSA_FORCE_OUTPUT_CNTL = 0x788C, - TMDSA_BIT_DEPTH_CONTROL = 0x7894, - TMDSA_DCBALANCER_CONTROL = 0x78D0, - TMDSA_DATA_SYNCHRONIZATION_R500 = 0x78D8, - TMDSA_DATA_SYNCHRONIZATION_R600 = 0x78DC, - TMDSA_TRANSMITTER_ENABLE = 0x7904, - TMDSA_LOAD_DETECT = 0x7908, - TMDSA_MACRO_CONTROL = 0x790C, /* r5x0 and r600: 3 for pll and 1 for TX */ - TMDSA_PLL_ADJUST = 0x790C, /* rv6x0: pll only */ - TMDSA_TRANSMITTER_CONTROL = 0x7910, - TMDSA_TRANSMITTER_ADJUST = 0x7920, /* rv6x0: TX part of macro control */ - - /* DAC B */ - DACB_ENABLE = 0x7A00, - DACB_SOURCE_SELECT = 0x7A04, - DACB_SYNC_TRISTATE_CONTROL = 0x7A20, - DACB_SYNC_SELECT = 0x7A24, - DACB_AUTODETECT_CONTROL = 0x7A28, - DACB_AUTODETECT_INT_CONTROL = 0x7A38, - DACB_FORCE_OUTPUT_CNTL = 0x7A3C, - DACB_FORCE_DATA = 0x7A40, - DACB_POWERDOWN = 0x7A50, - DACB_CONTROL1 = 0x7A54, - DACB_CONTROL2 = 0x7A58, - DACB_COMPARATOR_ENABLE = 0x7A5C, - DACB_COMPARATOR_OUTPUT = 0x7A60, - - /* LVTMA */ - LVTMA_CNTL = 0x7A80, - LVTMA_SOURCE_SELECT = 0x7A84, - LVTMA_COLOR_FORMAT = 0x7A88, - LVTMA_FORCE_OUTPUT_CNTL = 0x7A8C, - LVTMA_BIT_DEPTH_CONTROL = 0x7A94, - LVTMA_DCBALANCER_CONTROL = 0x7AD0, - - /* no longer shared between both r5xx and r6xx */ - LVTMA_R500_DATA_SYNCHRONIZATION = 0x7AD8, - LVTMA_R500_PWRSEQ_REF_DIV = 0x7AE4, - LVTMA_R500_PWRSEQ_DELAY1 = 0x7AE8, - LVTMA_R500_PWRSEQ_DELAY2 = 0x7AEC, - LVTMA_R500_PWRSEQ_CNTL = 0x7AF0, - LVTMA_R500_PWRSEQ_STATE = 0x7AF4, - LVTMA_R500_BL_MOD_CNTL = 0x7AF8, - LVTMA_R500_LVDS_DATA_CNTL = 0x7AFC, - LVTMA_R500_MODE = 0x7B00, - LVTMA_R500_TRANSMITTER_ENABLE = 0x7B04, - LVTMA_R500_MACRO_CONTROL = 0x7B0C, - LVTMA_R500_TRANSMITTER_CONTROL = 0x7B10, - LVTMA_R500_REG_TEST_OUTPUT = 0x7B14, - - /* R600 adds an undocumented register at 0x7AD8, - * shifting all subsequent registers by exactly one. */ - LVTMA_R600_DATA_SYNCHRONIZATION = 0x7ADC, - LVTMA_R600_PWRSEQ_REF_DIV = 0x7AE8, - LVTMA_R600_PWRSEQ_DELAY1 = 0x7AEC, - LVTMA_R600_PWRSEQ_DELAY2 = 0x7AF0, - LVTMA_R600_PWRSEQ_CNTL = 0x7AF4, - LVTMA_R600_PWRSEQ_STATE = 0x7AF8, - LVTMA_R600_BL_MOD_CNTL = 0x7AFC, - LVTMA_R600_LVDS_DATA_CNTL = 0x7B00, - LVTMA_R600_MODE = 0x7B04, - LVTMA_R600_TRANSMITTER_ENABLE = 0x7B08, - LVTMA_R600_MACRO_CONTROL = 0x7B10, - LVTMA_R600_TRANSMITTER_CONTROL = 0x7B14, - LVTMA_R600_REG_TEST_OUTPUT = 0x7B18, - - LVTMA_TRANSMITTER_ADJUST = 0x7B24, /* RV630 */ - LVTMA_PREEMPHASIS_CONTROL = 0x7B28, /* RV630 */ - - /* I2C in separate enum */ - - /* HPD */ - DC_GPIO_HPD_MASK = 0x7E90, - DC_GPIO_HPD_A = 0x7E94, - DC_GPIO_HPD_EN = 0x7E98, - DC_GPIO_HPD_Y = 0x7E9C -}; - -enum DXSCL_UPDATE_bits { - DXSCL_UPDATE_LOCK = (1 << 16) -}; - -enum CONFIG_CNTL_BITS { - RS69_CFG_ATI_REV_ID_SHIFT = 8, - RS69_CFG_ATI_REV_ID_MASK = 0xF << RS69_CFG_ATI_REV_ID_SHIFT -}; - -enum rv620Regs { - /* DAC common */ - RV620_DAC_COMPARATOR_MISC = 0x7da4, - RV620_DAC_COMPARATOR_OUTPUT = 0x7da8, - - /* RV620 DAC A */ - RV620_DACA_ENABLE = 0x7000, - RV620_DACA_SOURCE_SELECT = 0x7004, - RV620_DACA_SYNC_TRISTATE_CONTROL = 0x7020, - /* RV620_DACA_SYNC_SELECT = 0x7024, ?? */ - RV620_DACA_AUTODETECT_CONTROL = 0x7028, - RV620_DACA_AUTODETECT_STATUS = 0x7034, - RV620_DACA_AUTODETECT_INT_CONTROL = 0x7038, - RV620_DACA_FORCE_OUTPUT_CNTL = 0x703C, - RV620_DACA_FORCE_DATA = 0x7040, - RV620_DACA_POWERDOWN = 0x7050, - /* RV620_DACA_CONTROL1 moved */ - RV620_DACA_CONTROL2 = 0x7058, - RV620_DACA_COMPARATOR_ENABLE = 0x705C, - /* RV620_DACA_COMPARATOR_OUTPUT changed */ - RV620_DACA_BGADJ_SRC = 0x7ef0, - RV620_DACA_MACRO_CNTL = 0x7ef4, - RV620_DACA_AUTO_CALIB_CONTROL = 0x7ef8, - - /* DAC B */ - RV620_DACB_ENABLE = 0x7100, - RV620_DACB_SOURCE_SELECT = 0x7104, - RV620_DACB_SYNC_TRISTATE_CONTROL = 0x7120, - /* RV620_DACB_SYNC_SELECT = 0x7124, ?? */ - RV620_DACB_AUTODETECT_CONTROL = 0x7128, - RV620_DACB_AUTODETECT_STATUS = 0x7134, - RV620_DACB_AUTODETECT_INT_CONTROL = 0x7138, - RV620_DACB_FORCE_OUTPUT_CNTL = 0x713C, - RV620_DACB_FORCE_DATA = 0x7140, - RV620_DACB_POWERDOWN = 0x7150, - /* RV620_DACB_CONTROL1 moved */ - RV620_DACB_CONTROL2 = 0x7158, - RV620_DACB_COMPARATOR_ENABLE = 0x715C, - RV620_DACB_BGADJ_SRC = 0x7ef0, - RV620_DACB_MACRO_CNTL = 0x7ff4, - RV620_DACB_AUTO_CALIB_CONTROL = 0x7ef8, - /* DIG1 */ - RV620_DIG1_CNTL = 0x75A0, - RV620_DIG1_CLOCK_PATTERN = 0x75AC, - RV620_LVDS1_DATA_CNTL = 0x75BC, - RV620_TMDS1_CNTL = 0x75C0, - /* DIG2 */ - RV620_DIG2_CNTL = 0x79A0, - RV620_DIG2_CLOCK_PATTERN = 0x79AC, - RV620_LVDS2_DATA_CNTL = 0x79BC, - RV620_TMDS2_CNTL = 0x79C0, - - /* RV62x I2C */ - RV62_GENERIC_I2C_CONTROL = 0x7d80, /* (RW) */ - RV62_GENERIC_I2C_INTERRUPT_CONTROL = 0x7d84, /* (RW) */ - RV62_GENERIC_I2C_STATUS = 0x7d88, /* (RW) */ - RV62_GENERIC_I2C_SPEED = 0x7d8c, /* (RW) */ - RV62_GENERIC_I2C_SETUP = 0x7d90, /* (RW) */ - RV62_GENERIC_I2C_TRANSACTION = 0x7d94, /* (RW) */ - RV62_GENERIC_I2C_DATA = 0x7d98, /* (RW) */ - RV62_GENERIC_I2C_PIN_SELECTION = 0x7d9c, /* (RW) */ - RV62_DC_GPIO_DDC4_MASK = 0x7e20, /* (RW) */ - RV62_DC_GPIO_DDC1_MASK = 0x7e40, /* (RW) */ - RV62_DC_GPIO_DDC2_MASK = 0x7e50, /* (RW) */ - RV62_DC_GPIO_DDC3_MASK = 0x7e60, /* (RW) */ - - /* ?? */ - RV620_DCIO_LINK_STEER_CNTL = 0x7FA4, - - RV620_LVTMA_TRANSMITTER_CONTROL= 0x7F00, - RV620_LVTMA_TRANSMITTER_ENABLE = 0x7F04, - RV620_LVTMA_TRANSMITTER_ADJUST = 0x7F18, - RV620_LVTMA_PREEMPHASIS_CONTROL= 0x7F1C, - RV620_LVTMA_MACRO_CONTROL = 0x7F0C, - RV620_LVTMA_PWRSEQ_CNTL = 0x7F80, - RV620_LVTMA_PWRSEQ_STATE = 0x7f84, - RV620_LVTMA_PWRSEQ_REF_DIV = 0x7f88, - RV620_LVTMA_PWRSEQ_DELAY1 = 0x7f8C, - RV620_LVTMA_PWRSEQ_DELAY2 = 0x7f90, - RV620_LVTMA_BL_MOD_CNTL = 0x7F94, - RV620_LVTMA_DATA_SYNCHRONIZATION = 0x7F98, - RV620_FMT1_CONTROL = 0x6700, - RV620_FMT1_BIT_DEPTH_CONTROL= 0x6710, - RV620_FMT1_CLAMP_CNTL = 0x672C, - RV620_FMT2_CONTROL = 0x6F00, - RV620_FMT2_CNTL = 0x6F10, - RV620_FMT2_CLAMP_CNTL = 0x6F2C, - - RV620_EXT1_DIFF_POST_DIV_CNTL= 0x0420, - RV620_EXT2_DIFF_POST_DIV_CNTL= 0x0424, - RV620_DCCG_PCLK_DIGA_CNTL = 0x04b0, - RV620_DCCG_PCLK_DIGB_CNTL = 0x04b4, - RV620_DCCG_SYMCLK_CNTL = 0x04b8 -}; - -enum RV620_EXT1_DIFF_POST_DIV_CNTL_BITS { - RV62_EXT1_DIFF_POST_DIV_RESET = 1 << 0, - RV62_EXT1_DIFF_POST_DIV_SELECT = 1 << 4, - RV62_EXT1_DIFF_DRIVER_ENABLE = 1 << 8 -}; - -enum RV620_EXT2_DIFF_POST_DIV_CNTL_BITS { - RV62_EXT2_DIFF_POST_DIV_RESET = 1 << 0, - RV62_EXT2_DIFF_POST_DIV_SELECT = 1 << 4, - RV62_EXT2_DIFF_DRIVER_ENABLE = 3 << 8 -}; - -enum RV620_LVTMA_PWRSEQ_CNTL_BITS { - RV62_LVTMA_PWRSEQ_EN = 1 << 0, - RV62_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN = 1 << 1, - RV62_LVTMA_PLL_ENABLE_PWRSEQ_MASK = 1 << 2, - RV62_LVTMA_PLL_RESET_PWRSEQ_MASK = 1 << 3, - RV62_LVTMA_PWRSEQ_TARGET_STATE = 1 << 4, - RV62_LVTMA_SYNCEN = 1 << 8, - RV62_LVTMA_SYNCEN_OVRD = 1 << 9, - RV62_LVTMA_SYNCEN_POL = 1 << 10, - RV62_LVTMA_DIGON = 1 << 16, - RV62_LVTMA_DIGON_OVRD = 1 << 17, - RV62_LVTMA_DIGON_POL = 1 << 18, - RV62_LVTMA_BLON = 1 << 24, - RV62_LVTMA_BLON_OVRD = 1 << 25, - RV62_LVTMA_BLON_POL = 1 << 26 -}; - -enum RV620_LVTMA_PWRSEQ_STATE_BITS { - RV62_LVTMA_PWRSEQ_STATE_SHIFT = 8 -}; - -enum RV620_LVTMA_PWRSEQ_STATE_VAL { - RV62_POWERUP_DONE = 4, - RV62_POWERDOWN_DONE = 9 -}; - -enum RV620_LVTMA_TRANSMITTER_CONTROL_BITS { - RV62_LVTMA_PLL_ENABLE = 1 << 0, - RV62_LVTMA_PLL_RESET = 1 << 1, - RV62_LVTMA_IDSCKSEL = 1 << 4, - RV62_LVTMA_BGSLEEP = 1 << 5, - RV62_LVTMA_IDCLK_SEL = 1 << 6, - RV62_LVTMA_TMCLK = 1 << 8, - RV62_LVTMA_TMCLK_FROM_PADS = 1 << 13, - RV62_LVTMA_TDCLK = 1 << 14, - RV62_LVTMA_TDCLK_FROM_PADS = 1 << 15, - RV62_LVTMA_BYPASS_PLL = 1 << 28, - RV62_LVTMA_USE_CLK_DATA = 1 << 29, - RV62_LVTMA_MODE = 1 << 30, - RV62_LVTMA_INPUT_TEST_CLK_SEL = 1 << 31 -}; - -enum RV620_DCCG_SYMCLK_CNTL { - RV62_SYMCLKA_SRC_SHIFT = 8, - RV62_SYMCLKB_SRC_SHIFT = 12 -}; - -enum RV620_DCCG_DIG_CNTL { - RV62_PCLK_DIGA_ON = 0x1 -}; - -enum RV620_DCIO_LINK_STEER_CNTL { - RV62_LINK_STEER_SWAP = 1 << 0, - RV62_LINK_STEER_PLLSEL_OVERWRITE_EN = 1 << 16, - RV62_LINK_STEER_PLLSELA = 1 << 17, - RV62_LINK_STEER_PLLSELB = 1 << 18 -}; - -enum R620_LVTMA_TRANSMITTER_ENABLE_BITS { - RV62_LVTMA_LNK0EN = 1 << 0, - RV62_LVTMA_LNK1EN = 1 << 1, - RV62_LVTMA_LNK2EN = 1 << 2, - RV62_LVTMA_LNK3EN = 1 << 3, - RV62_LVTMA_LNK4EN = 1 << 4, - RV62_LVTMA_LNK5EN = 1 << 5, - RV62_LVTMA_LNK6EN = 1 << 6, - RV62_LVTMA_LNK7EN = 1 << 7, - RV62_LVTMA_LNK8EN = 1 << 8, - RV62_LVTMA_LNK9EN = 1 << 9, - RV62_LVTMA_LNKL = RV62_LVTMA_LNK0EN | RV62_LVTMA_LNK1EN - | RV62_LVTMA_LNK2EN | RV62_LVTMA_LNK3EN, - RV62_LVTMA_LNKU = RV62_LVTMA_LNK4EN | RV62_LVTMA_LNK5EN - | RV62_LVTMA_LNK6EN | RV62_LVTMA_LNK7EN, - RV62_LVTMA_LNK_ALL = RV62_LVTMA_LNKL | RV62_LVTMA_LNKU - | RV62_LVTMA_LNK8EN | RV62_LVTMA_LNK9EN, - RV62_LVTMA_LNKEN_HPD_MASK = 1 << 16 -}; - -enum RV620_LVTMA_DATA_SYNCHRONIZATION { - RV62_LVTMA_DSYNSEL = (1 << 0), - RV62_LVTMA_PFREQCHG = (1 << 8) -}; - -enum RV620_LVTMA_PWRSEQ_REF_DIV_BITS { - LVTMA_PWRSEQ_REF_DI_SHIFT = 0, - LVTMA_BL_MOD_REF_DI_SHIFT = 16 -}; - -enum RV620_LVTMA_BL_MOD_CNTL_BITS { - LVTMA_BL_MOD_EN = 1 << 0, - LVTMA_BL_MOD_LEVEL_SHIFT = 8, - LVTMA_BL_MOD_RES_SHIFT = 16 -}; - -enum RV620_DIG_CNTL_BITS { - /* 0x75A0 */ - RV62_DIG_SWAP = (0x1 << 16), - RV62_DIG_DUAL_LINK_ENABLE = (0x1 << 12), - RV62_DIG_START = (0x1 << 6), - RV62_DIG_MODE = (0x7 << 8), - RV62_DIG_STEREOSYNC_SELECT = (1 << 2), - RV62_DIG_SOURCE_SELECT = (1 << 0), - RV62_DIG_SOURCE_SELECT_FMT1 = (0 << 0), - RV62_DIG_SOURCE_SELECT_FMT2 = (1 << 0) -}; - -enum RV620_DIG_LVDS_DATA_CNTL_BITS { - /* 0x75BC */ - RV62_LVDS_24BIT_ENABLE = (0x1 << 0), - RV62_LVDS_24BIT_FORMAT = (0x1 << 4) -}; - -enum RV620_TMDS_CNTL_BITS { - /* 0x75C0 */ - RV62_TMDS_PIXEL_ENCODING = (0x1 << 4), - RV62_TMDS_COLOR_FORMAT = (0x3 << 8) -}; - -enum RV620_FMT_BIT_DEPTH_CONTROL { - RV62_FMT_TRUNCATE_EN = 1 << 0, - RV62_FMT_TRUNCATE_DEPTH = 1 << 4, - RV62_FMT_SPATIAL_DITHER_EN = 1 << 8, - RV62_FMT_SPATIAL_DITHER_MODE = 1 << 9, - RV62_FMT_SPATIAL_DITHER_DEPTH = 1 << 12, - RV62_FMT_FRAME_RANDOM_ENABLE = 1 << 13, - RV62_FMT_RGB_RANDOM_ENABLE = 1 << 14, - RV62_FMT_HIGHPASS_RANDOM_ENABLE = 1 << 15, - RV62_FMT_TEMPORAL_DITHER_EN = 1 << 16, - RV62_FMT_TEMPORAL_DITHER_DEPTH = 1 << 20, - RV62_FMT_TEMPORAL_DITHER_OFFSET = 3 << 21, - RV62_FMT_TEMPORAL_LEVEL = 1 << 24, - RV62_FMT_TEMPORAL_DITHER_RESET = 1 << 25, - RV62_FMT_25FRC_SEL = 3 << 26, - RV62_FMT_50FRC_SEL = 3 << 28, - RV62_FMT_75FRC_SEL = 3 << 30 -}; - -enum RV620_FMT_CONTROL { - RV62_FMT_PIXEL_ENCODING = 1 << 16 -}; - -enum _r5xxMCRegs { - R5XX_MC_STATUS = 0x0000, - RV515_MC_FB_LOCATION = 0x0001, - R5XX_MC_FB_LOCATION = 0x0004, - RV515_MC_STATUS = 0x0008, - RV515_MC_MISC_LAT_TIMER = 0x0009 -}; - -enum _r5xxRegs { - /* I2C */ - R5_DC_I2C_STATUS1 = 0x7D30, /* (RW) */ - R5_DC_I2C_RESET = 0x7D34, /* (RW) */ - R5_DC_I2C_CONTROL1 = 0x7D38, /* (RW) */ - R5_DC_I2C_CONTROL2 = 0x7D3C, /* (RW) */ - R5_DC_I2C_CONTROL3 = 0x7D40, /* (RW) */ - R5_DC_I2C_DATA = 0x7D44, /* (RW) */ - R5_DC_I2C_INTERRUPT_CONTROL = 0x7D48, /* (RW) */ - R5_DC_I2C_ARBITRATION = 0x7D50, /* (RW) */ - - R5_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */ - R5_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */ - R5_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */ - R5_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */ - R5_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */ - R5_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */ - R5_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */ - R5_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */ - R5_DC_GPIO_DDC3_EN = 0x7E68 /* (RW) */ -}; - -enum _r5xxSPLLRegs { - SPLL_FUNC_CNTL = 0x0 /* (RW) */ -}; - -enum _r6xxRegs { - /* MCLK */ - R6_MCLK_PWRMGT_CNTL = 0x620, - /* I2C */ - R6_DC_I2C_CONTROL = 0x7D30, /* (RW) */ - R6_DC_I2C_ARBITRATION = 0x7D34, /* (RW) */ - R6_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */ - R6_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) */ - R6_DC_I2C_DDC1_SPEED = 0x7D4C, /* (RW) */ - R6_DC_I2C_DDC1_SETUP = 0x7D50, /* (RW) */ - R6_DC_I2C_DDC2_SPEED = 0x7D54, /* (RW) */ - R6_DC_I2C_DDC2_SETUP = 0x7D58, /* (RW) */ - R6_DC_I2C_DDC3_SPEED = 0x7D5C, /* (RW) */ - R6_DC_I2C_DDC3_SETUP = 0x7D60, /* (RW) */ - R6_DC_I2C_TRANSACTION0 = 0x7D64, /* (RW) */ - R6_DC_I2C_TRANSACTION1 = 0x7D68, /* (RW) */ - R6_DC_I2C_DATA = 0x7D74, /* (RW) */ - R6_DC_I2C_DDC4_SPEED = 0x7DB4, /* (RW) */ - R6_DC_I2C_DDC4_SETUP = 0x7DBC, /* (RW) */ - R6_DC_GPIO_DDC4_MASK = 0x7E00, /* (RW) */ - R6_DC_GPIO_DDC4_A = 0x7E04, /* (RW) */ - R6_DC_GPIO_DDC4_EN = 0x7E08, /* (RW) */ - R6_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */ - R6_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */ - R6_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */ - R6_DC_GPIO_DDC1_Y = 0x7E4C, /* (RW) */ - R6_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */ - R6_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */ - R6_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */ - R6_DC_GPIO_DDC2_Y = 0x7E5C, /* (RW) */ - R6_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */ - R6_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */ - R6_DC_GPIO_DDC3_EN = 0x7E68, /* (RW) */ - R6_DC_GPIO_DDC3_Y = 0x7E6C /* (RW) */ -}; - -enum R6_MCLK_PWRMGT_CNTL { - R6_MC_BUSY = (1 << 5) -}; - - -/* *_Q: questionbable */ -enum _rs69xRegs { - /* I2C */ - RS69_DC_I2C_CONTROL = 0x7D30, /* (RW) *//* */ - RS69_DC_I2C_UNKNOWN_2 = 0x7D34, /* (RW) */ - RS69_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */ - RS69_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) *//**/ - RS69_DC_I2C_UNKNOWN_1 = 0x7d40, - RS69_DC_I2C_DDC_SETUP_Q = 0x7D44, /* (RW) */ - RS69_DC_I2C_DATA = 0x7D58, /* (RW) *//**/ - RS69_DC_I2C_TRANSACTION0 = 0x7D48, /* (RW) *//**/ - RS69_DC_I2C_TRANSACTION1 = 0x7D4C, /* (RW) *//**/ - /* DDIA */ - RS69_DDIA_CNTL = 0x7200, - RS69_DDIA_SOURCE_SELECT = 0x7204, - RS69_DDIA_BIT_DEPTH_CONTROL = 0x7214, - RS69_DDIA_DCBALANCER_CONTROL = 0x7250, - RS69_DDIA_PATH_CONTROL = 0x7264, - RS69_DDIA_PCIE_LINK_CONTROL2 = 0x7278, - RS69_DDIA_PCIE_LINK_CONTROL3 = 0x727c, - RS69_DDIA_PCIE_PHY_CONTROL1 = 0x728c, - RS69_DDIA_PCIE_PHY_CONTROL2 = 0x7290 -}; - -enum RS69_DDIA_CNTL_BITS { - RS69_DDIA_ENABLE = 1 << 0, - RS69_DDIA_HDMI_EN = 1 << 2, - RS69_DDIA_ENABLE_HPD_MASK = 1 << 4, - RS69_DDIA_HPD_SELECT = 1 << 8, - RS69_DDIA_SYNC_PHASE = 1 << 12, - RS69_DDIA_PIXEL_ENCODING = 1 << 16, - RS69_DDIA_DUAL_LINK_ENABLE = 1 << 24, - RS69_DDIA_SWAP = 1 << 28 -}; - -enum RS69_DDIA_SOURCE_SELECT_BITS { - RS69_DDIA_SOURCE_SELECT_BIT = 1 << 0, - RS69_DDIA_SYNC_SELECT = 1 << 8, - RS69_DDIA_STEREOSYNC_SELECT = 1 << 16 -}; - -enum RS69_DDIA_LINK_CONTROL2_SHIFT { - RS69_DDIA_PCIE_OUTPUT_MUX_SEL0 = 0, - RS69_DDIA_PCIE_OUTPUT_MUX_SEL1 = 4, - RS69_DDIA_PCIE_OUTPUT_MUX_SEL2 = 8, - RS69_DDIA_PCIE_OUTPUT_MUX_SEL3 = 12 -}; - -enum RS69_DDIA_BIT_DEPTH_CONTROL_BITS { - RS69_DDIA_TRUNCATE_EN = 1 << 0, - RS69_DDIA_TRUNCATE_DEPTH = 1 << 4, - RS69_DDIA_SPATIAL_DITHER_EN = 1 << 8, - RS69_DDIA_SPATIAL_DITHER_DEPTH = 1 << 12, - RS69_DDIA_TEMPORAL_DITHER_EN = 1 << 16, - RS69_DDIA_TEMPORAL_DITHER_DEPTH = 1 << 20, - RS69_DDIA_TEMPORAL_LEVEL = 1 << 24, - RS69_DDIA_TEMPORAL_DITHER_RESET = 1 << 25 -}; - -enum RS69_DDIA_DCBALANCER_CONTROL_BITS { - RS69_DDIA_DCBALANCER_EN = 1 << 0, - RS69_DDIA_SYNC_DCBAL_EN_SHIFT = 4, - RS69_DDIA_SYNC_DCBAL_EN_MASK = 7 << RS69_DDIA_SYNC_DCBAL_EN_SHIFT, - RS69_DDIA_DCBALANCER_TEST_EN = 1 << 8, - RS69_DDIA_DCBALANCER_TEST_IN_SHIFT = 16, - RS69_DDIA_DCBALANCER_FORCE = 1 << 24 -}; - -enum RS69_DDIA_PATH_CONTROL_BITS { - RS69_DDIA_PATH_SELECT_SHIFT = 0, - RS69_DDIA_DDPII_DE_ALIGN_EN = 1 << 4, - RS69_DDIA_DDPII_TRAIN_EN = 1 << 8, - RS69_DDIA_DDPII_TRAIN_SELECT = 1 << 12, - RS69_DDIA_DDPII_SCRAMBLE_EN = 1 << 16, - RS69_DDIA_REPL_MODE_SELECT = 1 << 20, - RS69_DDIA_RB_30b_SWAP_EN = 1 << 24, - RS69_DDIA_PIXVLD_RESET = 1 << 28, - RS69_DDIA_REARRANGER_EN = 1 << 30 -}; - -enum RS69_DDIA_PCIE_LINK_CONTROL3_BITS { - RS69_DDIA_PCIE_MIRROR_EN = 1 << 0, - RS69_DDIA_PCIE_CFGDUALLINK = 1 << 4, - RS69_DDIA_PCIE_NCHG3EN = 1 << 8, - RS69_DDIA_PCIE_RX_PDNB_SHIFT = 12 -}; - -enum RS69_MC_INDEX_BITS { - PCIE_RS69_MC_IND_ADDR = (0x1 << 0), - PCIE_RS69_MC_IND_WR_EN = (0x1 << 9) -}; - -enum RS60_MC_NB_MC_INDEX_BITS { - RS60_NB_MC_IND_ADDR = (0x1 << 0), - RS60_NB_MC_IND_WR_EN = (0x1 << 8) -}; - -enum _rs690MCRegs { - RS69_K8_FB_LOCATION = 0x1E, - RS69_MC_MISC_UMA_CNTL = 0x5f, - RS69_MC_SYSTEM_STATUS = 0x90, /* (RW) */ - RS69_MCCFG_FB_LOCATION = 0x100, - RS69MCCFG_AGP_LOCATION = 0x101, - RS69_MC_INIT_MISC_LAT_TIMER = 0x104 -}; - -enum MC_MISC_LAT_TIMER_BITS { - MC_CPR_INIT_LAT_SHIFT = 0, - MC_VF_INIT_LAT = 4, - MC_DISP0R_INIT_LAT_SHIFT = 8, - MC_DISP1R_INIT_LAT_SHIFT = 12, - MC_FIXED_INIT_LAT_SHIFT = 16, - MC_E2R_INIT_LAT_SHIFT = 20, - SAME_PAGE_PRIO_SHIFT = 24, - MC_GLOBW_INIT_LAT_SHIFT = 28 -}; - -enum RS69_MC_MISC_UMA_CNTL_BITS { - RS69_K8_40BIT_ADDR_EXTENSION = (0x1 << 0), - RS69_GART_BYPASS = (0x1 << 8), - RS69_GFX_64BYTE_MODE = (0x1 << 9), - RS69_GFX_64BYTE_LAT = (0x1 << 10), - RS69_GTW_COHERENCY = (0x1 << 15), - RS69_READ_BUFFER_SIZE = (0x1 << 16), - RS69_HDR_ROUTE_TO_DSP = (0x1 << 24), - RS69_GTW_ROUTE_TO_DSP = (0x1 << 25), - RS69_DSP_ROUTE_TO_GFX = (0x1 << 26), - RS69_USE_HDPW_LAT_INIT = (0x1 << 27), - RS69_USE_GFXW_LAT_INIT = (0x1 << 28), - RS69_MCIFR_COHERENT = (0x1 << 29), - RS69_NON_SNOOP_AZR_AIC_BP = (0x1 << 30), - RS69_SIDE_PORT_PRESENT_R = (0x1 << 31) -}; - -enum _rs600MCRegs { - RS60_MC_SYSTEM_STATUS = 0x0, - RS60_NB_FB_LOCATION = 0xa -}; - -enum RS600_MC_INDEX_BITS { - RS600_MC_INDEX_ADDR_MASK = 0xffff, - RS600_MC_INDEX_SEQ_RBS_0 = (1 << 16), - RS600_MC_INDEX_SEQ_RBS_1 = (1 << 17), - RS600_MC_INDEX_SEQ_RBS_2 = (1 << 18), - RS600_MC_INDEX_SEQ_RBS_3 = (1 << 19), - RS600_MC_INDEX_AIC_RBS = (1 << 20), - RS600_MC_INDEX_CITF_ARB0 = (1 << 21), - RS600_MC_INDEX_CITF_ARB1 = (1 << 22), - RS600_MC_INDEX_WR_EN = (1 << 23) -}; - -enum RS690_MC_INDEX_BITS { - RS690_MC_INDEX_ADDR_MASK = 0x1ff, - RS690_MC_INDEX_WR_EN = (1 << 9), - RS690_MC_INDEX_WR_ACK = 0x7f -}; - -enum RS780_MC_INDEX_BITS { - RS780_MC_INDEX_ADDR_MASK = 0x1ff, - RS780_MC_INDEX_WR_EN = (1 << 9) -}; - -enum _rs780NBRegs { - PCIE_RS78_NB_MC_IND_INDEX = 0x70, - PCIE_RS78_NB_MC_IND_DATA = 0x74 -}; - -enum RS78_NB_IND_INDEX_BITS { - PCIE_RS78_NB_MC_IND_INDEX_MASK = (0xffff << 0), - PCIE_RS78_MC_IND_SEQ_RBS_0 = (0x1 << 16), - PCIE_RS78_MC_IND_SEQ_RBS_1 = (0x1 << 17), - PCIE_RS78_MC_IND_SEQ_RBS_2 = (0x1 << 18), - PCIE_RS78_MC_IND_SEQ_RBS_3 = (0x1 << 19), - PCIE_RS78_MC_IND_AIC_RBS = (0x1 << 20), - PCIE_RS78_MC_IND_CITF_ARB0 = (0x1 << 21), - PCIE_RS78_MC_IND_CITF_ARB1 = (0x1 << 22), - PCIE_RS78_MC_IND_WR_EN = (0x1 << 23), - PCIE_RS78_MC_IND_RD_INV = (0x1 << 24) -}; - -enum _rs780MCRegs { - RS78_MC_SYSTEM_STATUS = 0x0, - RS78_MC_FB_LOCATION = 0x10, - RS78_K8_FB_LOCATION = 0x11, - RS78_MC_MISC_UMA_CNTL = 0x12 -}; - -enum RS6X_MC_SYSTEM_STATUS_BITS { - RS6X_MC_SYSTEM_IDLE = (0x1 << 0), - RS6X_MC_SEQUENCER_IDLE = (0x1 << 1), - RS6X_MC_ARBITER_IDLE = (0x1 << 2), - RS6X_MC_SELECT_PM = (0x1 << 3), - RS6X_RESERVED4 = (0xf << 4), - RS6X_RESERVED8 = (0xf << 8), - RS6X_RESERVED12_SYSTEM_STATUS = (0xf << 12), - RS6X_MCA_INIT_EXECUTED = (0x1 << 16), - RS6X_MCA_IDLE = (0x1 << 17), - RS6X_MCA_SEQ_IDLE = (0x1 << 18), - RS6X_MCA_ARB_IDLE = (0x1 << 19), - RS6X_RESERVED20_SYSTEM_STATUS = (0xfff << 20) -}; - -enum RS78_MC_MISC_UMA_CNTL_BITS { - RS78_K8_40BIT_ADDR_EXTENSION = ( 0x1 << 0), - RS78_BANKGROUP_SEL = ( 0x1 << 8), - RS78_CNTL_SPARE = ( 0x1 << 15), - RS78_SIDE_PORT_PRESENT_R = ( 0x1 << 31) -}; - -enum R5XX_MC_STATUS_BITS { - R5XX_MEM_PWRUP_COMPL = (0x1 << 0), - R5XX_MC_IDLE = (0x1 << 1) -}; - -enum RV515_MC_STATUS_BITS { - RV515_MC_IDLE = (0x1 << 4) -}; - -enum RS78_MC_SYSTEM_STATUS_BITS { - RS78_MC_SYSTEM_IDLE = 1 << 0, - RS78_MC_SEQUENCER_IDLE = 1 << 1, - RS78_MC_ARBITER_IDLE = 1 << 2, - RS78_MC_SELECT_PM = 1 << 3, - RS78_MC_STATUS_15_4_SHIFT = 4, - RS78_MCA_INIT_EXECUTED = 1 << 16, - RS78_MCA_IDLE = 1 << 17, - RS78_MCA_SEQ_IDLE = 1 << 18, - RS78_MCA_ARB_IDLE = 1 << 19, - RS78_MC_STATUS_31_20_SHIFT = 20 -}; - -enum BUS_CNTL_BITS { - /* BUS_CNTL */ - BUS_DBL_RESYNC = (0x1 << 0), - BIOS_ROM_WRT_EN = (0x1 << 1), - BIOS_ROM_DIS = (0x1 << 2), - PMI_IO_DIS = (0x1 << 3), - PMI_MEM_DIS = (0x1 << 4), - PMI_BM_DIS = (0x1 << 5), - PMI_INT_DIS = (0x1 << 6) -}; - -enum SEPROM_SNTL1_BITS { - /* SEPROM_CNTL1 */ - WRITE_ENABLE = (0x1 << 0), - WRITE_DISABLE = (0x1 << 1), - READ_CONFIG = (0x1 << 2), - WRITE_CONFIG = (0x1 << 3), - READ_STATUS = (0x1 << 4), - SECT_TO_SRAM = (0x1 << 5), - READY_BUSY = (0x1 << 7), - SEPROM_BUSY = (0x1 << 8), - BCNT_OVER_WTE_EN = (0x1 << 9), - RB_MASKB = (0x1 << 10), - SOFT_RESET = (0x1 << 11), - STATE_IDLEb = (0x1 << 12), - SECTOR_ERASE = (0x1 << 13), - BYTE_CNT = (0xff << 16), - SCK_PRESCALE = (0xff << 24) -}; - -enum VIPH_CONTROL_BITS { - /* VIPH_CONTROL */ - VIPH_CLK_SEL = (0xff << 0), - VIPH_REG_RDY = (0x1 << 13), - VIPH_MAX_WAIT = (0xf << 16), - VIPH_DMA_MODE = (0x1 << 20), - VIPH_EN = (0x1 << 21), - VIPH_DV0_WID = (0x1 << 24), - VIPH_DV1_WID = (0x1 << 25), - VIPH_DV2_WID = (0x1 << 26), - VIPH_DV3_WID = (0x1 << 27), - VIPH_PWR_DOWN = (0x1 << 28), - VIPH_PWR_DOWN_AK = (0x1 << 28), - VIPH_VIPCLK_DIS = (0x1 << 29) -}; - -enum ROM_CNTL_BITS { - SCK_OVERWRITE = 1 << 1, - CLOCK_GATING_EN = 1 << 2, - CSB_ACTIVE_TO_SCK_SETUP_TIME_SHIFT = 8, - CSB_ACTIVE_TO_SCK_HOLD_TIME_SHIFT = 16, - SCK_PRESCALE_REFCLK_SHIFT = 24, - SCK_PRESCALE_CRYSTAL_CLK_SHIFT = 28 -}; - -enum GENERAL_PWRMGT_BITS { - GLOBAL_PWRMGT_EN = 1 << 0, - STATIC_PM_EN = 1 << 1, - MOBILE_SU = 1 << 2, - THERMAL_PROTECTION_DIS = 1 << 3, - THERMAL_PROTECTION_TYPE = 1 << 4, - ENABLE_GEN2PCIE = 1 << 5, - SW_GPIO_INDEX_SHIFT = 1 << 6, - LOW_VOLT_D2_ACPI = 1 << 8, - LOW_VOLT_D3_ACPI = 1 << 9, - VOLT_PWRMGT_EN = 1 << 10, - OPEN_DRAIN_PADS = 1 << 11, - AVP_SCLK_EN = 1 << 12, - IDCT_SCLK_EN = 1 << 13, - GPU_COUNTER_ACPI = 1 << 14, - GPU_COUNTER_CLK = 1 << 15, - BACKBIAS_PAD_EN = 1 << 16, - BACKBIAS_VALUE = 1 << 17, - BACKBIAS_DPM_CNTL = 1 << 18, - SPREAD_SPECTRUM_INDEX_SHIFT = 19, - DYN_SPREAD_SPECTRUM_EN = 1 << 2 -}; - -enum VGA_RENDER_CONTROL_BITS { - /* VGA_RENDER_CONTROL */ - VGA_BLINK_RATE = (0x1f << 0), - VGA_BLINK_MODE = (0x3 << 5), - VGA_CURSOR_BLINK_INVERT = (0x1 << 7), - VGA_EXTD_ADDR_COUNT_ENABLE = (0x1 << 8), - VGA_VSTATUS_CNTL = (0x3 << 16), - VGA_LOCK_8DOT = (0x1 << 24), - VGAREG_LINECMP_COMPATIBILITY_SEL = (0x1 << 25) -}; - -enum D1VGA_CONTROL_BITS { - /* D1VGA_CONTROL */ - D1VGA_MODE_ENABLE = (0x1 << 0), - D1VGA_TIMING_SELECT = (0x1 << 8), - D1VGA_SYNC_POLARITY_SELECT = (0x1 << 9), - D1VGA_OVERSCAN_TIMING_SELECT = (0x1 << 10), - D1VGA_OVERSCAN_COLOR_EN = (0x1 << 16), - D1VGA_ROTATE = (0x3 << 24) -}; - -enum D2VGA_CONTROL_BITS { - /* D2VGA_CONTROL */ - D2VGA_MODE_ENABLE = (0x1 << 0), - D2VGA_TIMING_SELECT = (0x1 << 8), - D2VGA_SYNC_POLARITY_SELECT = (0x1 << 9), - D2VGA_OVERSCAN_TIMING_SELECT = (0x1 << 10), - D2VGA_OVERSCAN_COLOR_EN = (0x1 << 16), - D2VGA_ROTATE = (0x3 << 24) -}; - -enum { - /* CLOCK_CNTL_INDEX */ - PLL_ADDR = (0x3f << 0), - PLL_WR_EN = (0x1 << 7), - PPLL_DIV_SEL = (0x3 << 8), - - /* CLOCK_CNTL_DATA */ -#define PLL_DATA 0xffffffff - - /* SPLL_FUNC_CNTL */ - SPLL_CHG_STATUS = (0x1 << 29), - SPLL_BYPASS_EN = (0x1 << 25), - - /* MC_IND_INDEX */ - MC_IND_ADDR = (0xffff << 0), - MC_IND_SEQ_RBS_0 = (0x1 << 16), - MC_IND_SEQ_RBS_1 = (0x1 << 17), - MC_IND_SEQ_RBS_2 = (0x1 << 18), - MC_IND_SEQ_RBS_3 = (0x1 << 19), - MC_IND_AIC_RBS = (0x1 << 20), - MC_IND_CITF_ARB0 = (0x1 << 21), - MC_IND_CITF_ARB1 = (0x1 << 22), - MC_IND_WR_EN = (0x1 << 23), - MC_IND_RD_INV = (0x1 << 24) -#define MC_IND_ALL (MC_IND_SEQ_RBS_0 | MC_IND_SEQ_RBS_1 \ - | MC_IND_SEQ_RBS_2 | MC_IND_SEQ_RBS_3 \ - | MC_IND_AIC_RBS | MC_IND_CITF_ARB0 | MC_IND_CITF_ARB1) - - /* MC_IND_DATA */ -#define MC_IND_DATA_BIT 0xffffffff -}; - -enum AGP_STATUS_BITS { - AGP_1X_MODE = 0x01, - AGP_2X_MODE = 0x02, - AGP_4X_MODE = 0x04, - AGP_FW_MODE = 0x10, - AGP_MODE_MASK = 0x17, - AGPv3_MODE = 0x08, - AGPv3_4X_MODE = 0x01, - AGPv3_8X_MODE = 0x02 -}; - -enum { - /* HDMI registers */ - HDMI_ENABLE = 0x00, - HDMI_STATUS = 0x04, - HDMI_CNTL = 0x08, - HDMI_UNKNOWN_0 = 0x0C, - HDMI_AUDIOCNTL = 0x10, - HDMI_VIDEOCNTL = 0x14, - HDMI_VERSION = 0x18, - HDMI_UNKNOWN_1 = 0x28, - HDMI_VIDEOINFOFRAME_0 = 0x54, - HDMI_VIDEOINFOFRAME_1 = 0x58, - HDMI_VIDEOINFOFRAME_2 = 0x5c, - HDMI_VIDEOINFOFRAME_3 = 0x60, - HDMI_32kHz_CTS = 0xac, - HDMI_32kHz_N = 0xb0, - HDMI_44_1kHz_CTS = 0xb4, - HDMI_44_1kHz_N = 0xb8, - HDMI_48kHz_CTS = 0xbc, - HDMI_48kHz_N = 0xc0, - HDMI_AUDIOINFOFRAME_0 = 0xcc, - HDMI_AUDIOINFOFRAME_1 = 0xd0, - HDMI_IEC60958_1 = 0xd4, - HDMI_IEC60958_2 = 0xd8, - HDMI_UNKNOWN_2 = 0xdc, - HDMI_AUDIO_DEBUG_0 = 0xe0, - HDMI_AUDIO_DEBUG_1 = 0xe4, - HDMI_AUDIO_DEBUG_2 = 0xe8, - HDMI_AUDIO_DEBUG_3 = 0xec -}; - -#endif /* _RHD_REGS_H */ diff --git a/src/add-ons/accelerants/radeon_hd/accelerant.h b/src/add-ons/accelerants/radeon_hd/accelerant.h index a8bd40ebc0..ea4c0a42a4 100644 --- a/src/add-ons/accelerants/radeon_hd/accelerant.h +++ b/src/add-ons/accelerants/radeon_hd/accelerant.h @@ -73,9 +73,9 @@ struct accelerant_info { struct register_info { + uint16 crtcOffset; uint16 vgaControl; uint16 grphEnable; - uint16 grphUpdate; uint16 grphControl; uint16 grphSwapControl; uint16 grphPrimarySurfaceAddr; @@ -89,26 +89,10 @@ struct register_info { uint16 grphYStart; uint16 grphXEnd; uint16 grphYEnd; - uint16 crtControl; - uint16 crtCountControl; - uint16 crtInterlace; - uint16 crtHPolarity; - uint16 crtVPolarity; - uint16 crtHSync; - uint16 crtVSync; - uint16 crtHBlank; - uint16 crtVBlank; - uint16 crtHTotal; - uint16 crtVTotal; - uint16 crtcOffset; uint16 modeDesktopHeight; uint16 modeDataFormat; - uint16 modeCenter; uint16 viewportStart; uint16 viewportSize; - uint16 sclUpdate; - uint16 sclEnable; - uint16 sclTapControl; }; diff --git a/src/add-ons/accelerants/radeon_hd/display.cpp b/src/add-ons/accelerants/radeon_hd/display.cpp index bd75bf0cf1..408b978185 100644 --- a/src/add-ons/accelerants/radeon_hd/display.cpp +++ b/src/add-ons/accelerants/radeon_hd/display.cpp @@ -34,7 +34,7 @@ extern "C" void _sPrintf(const char *format, ...); /*! Populate regs with device dependant register locations */ status_t -init_registers(register_info* regs, uint8 crtid) +init_registers(register_info* regs, uint8 crtcID) { memset(regs, 0, sizeof(register_info)); @@ -43,112 +43,157 @@ init_registers(register_info* regs, uint8 crtid) if (info.device_chipset >= RADEON_R1000) { uint32 offset = 0; - // AMD Eyefinity on Evergreen GPUs - if (crtid == 1) { - offset = EVERGREEN_CRTC1_REGISTER_OFFSET; - regs->vgaControl = D2VGA_CONTROL; - } else if (crtid == 2) { - offset = EVERGREEN_CRTC2_REGISTER_OFFSET; - regs->vgaControl = EVERGREEN_D3VGA_CONTROL; - } else if (crtid == 3) { - offset = EVERGREEN_CRTC3_REGISTER_OFFSET; - regs->vgaControl = EVERGREEN_D4VGA_CONTROL; - } else if (crtid == 4) { - offset = EVERGREEN_CRTC4_REGISTER_OFFSET; - regs->vgaControl = EVERGREEN_D5VGA_CONTROL; - } else if (crtid == 5) { - offset = EVERGREEN_CRTC5_REGISTER_OFFSET; - regs->vgaControl = EVERGREEN_D6VGA_CONTROL; - } else { - offset = EVERGREEN_CRTC0_REGISTER_OFFSET; - regs->vgaControl = D1VGA_CONTROL; + switch(crtcID) { + case 0: + offset = EVERGREEN_CRTC0_REGISTER_OFFSET; + regs->vgaControl = AVIVO_D1VGA_CONTROL; + break; + case 1: + offset = EVERGREEN_CRTC1_REGISTER_OFFSET; + regs->vgaControl = AVIVO_D2VGA_CONTROL; + break; + case 2: + offset = EVERGREEN_CRTC2_REGISTER_OFFSET; + regs->vgaControl = EVERGREEN_D3VGA_CONTROL; + break; + case 3: + offset = EVERGREEN_CRTC3_REGISTER_OFFSET; + regs->vgaControl = EVERGREEN_D4VGA_CONTROL; + break; + case 4: + offset = EVERGREEN_CRTC4_REGISTER_OFFSET; + regs->vgaControl = EVERGREEN_D5VGA_CONTROL; + break; + case 5: + offset = EVERGREEN_CRTC5_REGISTER_OFFSET; + regs->vgaControl = EVERGREEN_D6VGA_CONTROL; + break; + default: + ERROR("%s: Unknown CRTC %" B_PRIu32 "\n", + __func__, crtcID); + return B_ERROR; } regs->crtcOffset = offset; - // Evergreen+ is crtoffset + register - regs->grphEnable = offset + EVERGREEN_GRPH_ENABLE; - regs->grphControl = offset + EVERGREEN_GRPH_CONTROL; - regs->grphSwapControl = offset + EVERGREEN_GRPH_SWAP_CONTROL; + regs->grphEnable = EVERGREEN_GRPH_ENABLE + offset; + regs->grphControl = EVERGREEN_GRPH_CONTROL + offset; + regs->grphSwapControl = EVERGREEN_GRPH_SWAP_CONTROL + offset; regs->grphPrimarySurfaceAddr - = offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS; + = EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + offset; regs->grphSecondarySurfaceAddr - = offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS; + = EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + offset; regs->grphPrimarySurfaceAddrHigh - = offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; + = EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + offset; regs->grphSecondarySurfaceAddrHigh - = offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; + = EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + offset; - regs->grphPitch = offset + EVERGREEN_GRPH_PITCH; + regs->grphPitch = EVERGREEN_GRPH_PITCH + offset; regs->grphSurfaceOffsetX - = offset + EVERGREEN_GRPH_SURFACE_OFFSET_X; + = EVERGREEN_GRPH_SURFACE_OFFSET_X + offset; regs->grphSurfaceOffsetY - = offset + EVERGREEN_GRPH_SURFACE_OFFSET_Y; - regs->grphXStart = offset + EVERGREEN_GRPH_X_START; - regs->grphYStart = offset + EVERGREEN_GRPH_Y_START; - regs->grphXEnd = offset + EVERGREEN_GRPH_X_END; - regs->grphYEnd = offset + EVERGREEN_GRPH_Y_END; - regs->crtControl = offset + EVERGREEN_CRTC_CONTROL; - regs->modeDesktopHeight = offset + EVERGREEN_DESKTOP_HEIGHT; - regs->modeDataFormat = offset + EVERGREEN_DATA_FORMAT; - regs->viewportStart = offset + EVERGREEN_VIEWPORT_START; - regs->viewportSize = offset + EVERGREEN_VIEWPORT_SIZE; + = EVERGREEN_GRPH_SURFACE_OFFSET_Y + offset; + regs->grphXStart = EVERGREEN_GRPH_X_START + offset; + regs->grphYStart = EVERGREEN_GRPH_Y_START + offset; + regs->grphXEnd = EVERGREEN_GRPH_X_END + offset; + regs->grphYEnd = EVERGREEN_GRPH_Y_END + offset; + regs->modeDesktopHeight = EVERGREEN_DESKTOP_HEIGHT + offset; + regs->modeDataFormat = EVERGREEN_DATA_FORMAT + offset; + regs->viewportStart = EVERGREEN_VIEWPORT_START + offset; + regs->viewportSize = EVERGREEN_VIEWPORT_SIZE + offset; - } else if (info.device_chipset >= RADEON_R600 - && info.device_chipset < RADEON_R1000) { + } else if (info.device_chipset >= RADEON_R700) { + uint32 offset = 0; + + switch(crtcID) { + case 0: + offset = R600_CRTC0_REGISTER_OFFSET; + regs->vgaControl = AVIVO_D1VGA_CONTROL; + regs->grphPrimarySurfaceAddrHigh + = D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; + break; + case 1: + offset = R600_CRTC1_REGISTER_OFFSET; + regs->vgaControl = AVIVO_D2VGA_CONTROL; + regs->grphPrimarySurfaceAddrHigh + = D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; + break; + default: + ERROR("%s: Unknown CRTC %" B_PRIu32 "\n", + __func__, crtcID); + return B_ERROR; + } + + regs->crtcOffset = offset; + + regs->grphEnable = AVIVO_D1GRPH_ENABLE + offset; + regs->grphControl = AVIVO_D1GRPH_CONTROL + offset; + regs->grphSwapControl = D1GRPH_SWAP_CNTL + offset; - // r600 - r700 are D1 or D2 based on primary / secondary crt - regs->vgaControl - = crtid == 1 ? D2VGA_CONTROL : D1VGA_CONTROL; - regs->grphEnable - = crtid == 1 ? D2GRPH_ENABLE : D1GRPH_ENABLE; - regs->grphControl - = crtid == 1 ? D2GRPH_CONTROL : D1GRPH_CONTROL; - regs->grphSwapControl - = crtid == 1 ? D2GRPH_SWAP_CNTL : D1GRPH_SWAP_CNTL; regs->grphPrimarySurfaceAddr - = crtid == 1 ? D2GRPH_PRIMARY_SURFACE_ADDRESS - : D1GRPH_PRIMARY_SURFACE_ADDRESS; + = D1GRPH_PRIMARY_SURFACE_ADDRESS + offset; regs->grphSecondarySurfaceAddr - = crtid == 1 ? D2GRPH_SECONDARY_SURFACE_ADDRESS - : D1GRPH_SECONDARY_SURFACE_ADDRESS; + = D1GRPH_SECONDARY_SURFACE_ADDRESS + offset; - regs->crtcOffset - = crtid == 1 ? (D2GRPH_X_END - D1GRPH_X_END) : 0; + regs->grphPitch = AVIVO_D1GRPH_PITCH + offset; + regs->grphSurfaceOffsetX = AVIVO_D1GRPH_SURFACE_OFFSET_X + offset; + regs->grphSurfaceOffsetY = AVIVO_D1GRPH_SURFACE_OFFSET_Y + offset; + regs->grphXStart = AVIVO_D1GRPH_X_START + offset; + regs->grphYStart = AVIVO_D1GRPH_Y_START + offset; + regs->grphXEnd = AVIVO_D1GRPH_X_END + offset; + regs->grphYEnd = AVIVO_D1GRPH_Y_END + offset; - // Surface Address high only used on r770+ - regs->grphPrimarySurfaceAddrHigh - = crtid == 1 ? D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH - : D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; - regs->grphSecondarySurfaceAddrHigh - = crtid == 1 ? D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH - : D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; + regs->modeDesktopHeight = AVIVO_D1MODE_DESKTOP_HEIGHT + offset; + regs->modeDataFormat = AVIVO_D1MODE_DATA_FORMAT + offset; + regs->viewportStart = AVIVO_D1MODE_VIEWPORT_START + offset; + regs->viewportSize = AVIVO_D1MODE_VIEWPORT_SIZE + offset; - regs->grphPitch - = crtid == 1 ? D2GRPH_PITCH : D1GRPH_PITCH; - regs->grphSurfaceOffsetX - = crtid == 1 ? D2GRPH_SURFACE_OFFSET_X : D1GRPH_SURFACE_OFFSET_X; - regs->grphSurfaceOffsetY - = crtid == 1 ? D2GRPH_SURFACE_OFFSET_Y : D1GRPH_SURFACE_OFFSET_Y; - regs->grphXStart - = crtid == 1 ? D2GRPH_X_START : D1GRPH_X_START; - regs->grphYStart - = crtid == 1 ? D2GRPH_Y_START : D1GRPH_Y_START; - regs->grphXEnd - = crtid == 1 ? D2GRPH_X_END : D1GRPH_X_END; - regs->grphYEnd - = crtid == 1 ? D2GRPH_Y_END : D1GRPH_Y_END; - regs->crtControl - = crtid == 1 ? D2CRTC_CONTROL : D1CRTC_CONTROL; - regs->modeDesktopHeight - = crtid == 1 ? D2MODE_DESKTOP_HEIGHT : D1MODE_DESKTOP_HEIGHT; - regs->modeDataFormat - = crtid == 1 ? D2MODE_DATA_FORMAT : D1MODE_DATA_FORMAT; - regs->viewportStart - = crtid == 1 ? D2MODE_VIEWPORT_START : D1MODE_VIEWPORT_START; - regs->viewportSize - = crtid == 1 ? D2MODE_VIEWPORT_SIZE : D1MODE_VIEWPORT_SIZE; + } else if (info.device_chipset >= RADEON_R600) { + uint32 offset = 0; + + switch(crtcID) { + case 0: + offset = R600_CRTC0_REGISTER_OFFSET; + regs->vgaControl = AVIVO_D1VGA_CONTROL; + break; + case 1: + offset = R600_CRTC1_REGISTER_OFFSET; + regs->vgaControl = AVIVO_D2VGA_CONTROL; + break; + default: + ERROR("%s: Unknown CRTC %" B_PRIu32 "\n", + __func__, crtcID); + return B_ERROR; + } + + regs->crtcOffset = offset; + + regs->grphEnable = AVIVO_D1GRPH_ENABLE + offset; + regs->grphControl = AVIVO_D1GRPH_CONTROL + offset; + regs->grphSwapControl = D1GRPH_SWAP_CNTL + offset; + + regs->grphPrimarySurfaceAddr + = D1GRPH_PRIMARY_SURFACE_ADDRESS + offset; + regs->grphSecondarySurfaceAddr + = D1GRPH_SECONDARY_SURFACE_ADDRESS + offset; + + // Surface Address high only used on r700 and higher + regs->grphPrimarySurfaceAddrHigh = 0xDEAD; + regs->grphSecondarySurfaceAddrHigh = 0xDEAD; + + regs->grphPitch = AVIVO_D1GRPH_PITCH + offset; + regs->grphSurfaceOffsetX = AVIVO_D1GRPH_SURFACE_OFFSET_X + offset; + regs->grphSurfaceOffsetY = AVIVO_D1GRPH_SURFACE_OFFSET_Y + offset; + regs->grphXStart = AVIVO_D1GRPH_X_START + offset; + regs->grphYStart = AVIVO_D1GRPH_Y_START + offset; + regs->grphXEnd = AVIVO_D1GRPH_X_END + offset; + regs->grphYEnd = AVIVO_D1GRPH_Y_END + offset; + + regs->modeDesktopHeight = AVIVO_D1MODE_DESKTOP_HEIGHT + offset; + regs->modeDataFormat = AVIVO_D1MODE_DATA_FORMAT + offset; + regs->viewportStart = AVIVO_D1MODE_VIEWPORT_START + offset; + regs->viewportSize = AVIVO_D1MODE_VIEWPORT_SIZE + offset; } else { // this really shouldn't happen unless a driver PCIID chipset is wrong TRACE("%s, unknown Radeon chipset: r%X\n", __func__, @@ -156,42 +201,8 @@ init_registers(register_info* regs, uint8 crtid) return B_ERROR; } - // Populate common registers - // TODO: Wait.. this doesn't work with Eyefinity > crt 1. - - regs->modeCenter - = crtid == 1 ? D2MODE_CENTER : D1MODE_CENTER; - regs->grphUpdate - = crtid == 1 ? D2GRPH_UPDATE : D1GRPH_UPDATE; - regs->crtHPolarity - = crtid == 1 ? D2CRTC_H_SYNC_A_CNTL : D1CRTC_H_SYNC_A_CNTL; - regs->crtVPolarity - = crtid == 1 ? D2CRTC_V_SYNC_A_CNTL : D1CRTC_V_SYNC_A_CNTL; - regs->crtHTotal - = crtid == 1 ? D2CRTC_H_TOTAL : D1CRTC_H_TOTAL; - regs->crtVTotal - = crtid == 1 ? D2CRTC_V_TOTAL : D1CRTC_V_TOTAL; - regs->crtHSync - = crtid == 1 ? D2CRTC_H_SYNC_A : D1CRTC_H_SYNC_A; - regs->crtVSync - = crtid == 1 ? D2CRTC_V_SYNC_A : D1CRTC_V_SYNC_A; - regs->crtHBlank - = crtid == 1 ? D2CRTC_H_BLANK_START_END : D1CRTC_H_BLANK_START_END; - regs->crtVBlank - = crtid == 1 ? D2CRTC_V_BLANK_START_END : D1CRTC_V_BLANK_START_END; - regs->crtInterlace - = crtid == 1 ? D2CRTC_INTERLACE_CONTROL : D1CRTC_INTERLACE_CONTROL; - regs->crtCountControl - = crtid == 1 ? D2CRTC_COUNT_CONTROL : D1CRTC_COUNT_CONTROL; - regs->sclUpdate - = crtid == 1 ? D2SCL_UPDATE : D1SCL_UPDATE; - regs->sclEnable - = crtid == 1 ? D2SCL_ENABLE : D1SCL_ENABLE; - regs->sclTapControl - = crtid == 1 ? D2SCL_TAP_CONTROL : D1SCL_TAP_CONTROL; - TRACE("%s, registers for ATI chipset r%X crt #%d loaded\n", __func__, - info.device_chipset, crtid); + info.device_chipset, crtcID); return B_OK; } @@ -943,11 +954,10 @@ display_crtc_fb_set(uint8 crtcID, display_mode *mode) Write32(OUT, regs->vgaControl, 0); uint64 fbAddress = gInfo->mc.vramStart; - //uint64 fbAddress = gInfo->shared_info->frame_buffer_phys; TRACE("%s: Framebuffer at: 0x%" B_PRIX64 "\n", __func__, fbAddress); - if (info.device_chipset >= (RADEON_R700 | 0x70)) { + if (info.device_chipset >= RADEON_R700) { TRACE("%s: Set SurfaceAddress High: 0x%" B_PRIX32 "\n", __func__, (fbAddress >> 32) & 0xf); diff --git a/src/add-ons/accelerants/radeon_hd/gpu.cpp b/src/add-ons/accelerants/radeon_hd/gpu.cpp index 4ace4dfa47..b920913ee4 100644 --- a/src/add-ons/accelerants/radeon_hd/gpu.cpp +++ b/src/add-ons/accelerants/radeon_hd/gpu.cpp @@ -242,7 +242,7 @@ radeon_gpu_mc_setup_r600() // idle the memory controller radeon_gpu_mc_halt(); - + uint32 idleState = radeon_gpu_mc_idlecheck(); if (idleState > 0) { ERROR("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n", @@ -260,7 +260,74 @@ radeon_gpu_mc_setup_r600() uint32 tmp = ((gInfo->mc.vramEnd >> 24) & 0xFFFF) << 16; tmp |= ((gInfo->mc.vramStart >> 24) & 0xFFFF); - Write32(OUT, R6XX_MC_VM_FB_LOCATION, tmp); + Write32(OUT, R600_MC_VM_FB_LOCATION, tmp); + Write32(OUT, HDP_NONSURFACE_BASE, (gInfo->mc.vramStart >> 8)); + Write32(OUT, HDP_NONSURFACE_INFO, (2 << 7)); + Write32(OUT, HDP_NONSURFACE_SIZE, 0x3FFFFFFF); + + // TODO: AGP gtt start / end / agp base + // is AGP? + // WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); + // WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); + // WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); + // else? + Write32(OUT, R600_MC_VM_AGP_BASE, 0); + Write32(OUT, R600_MC_VM_AGP_TOP, 0x0FFFFFFF); + Write32(OUT, R600_MC_VM_AGP_BOT, 0x0FFFFFFF); + + idleState = radeon_gpu_mc_idlecheck(); + if (idleState > 0) { + ERROR("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n", + __func__, idleState); + //return B_ERROR; + } + radeon_gpu_mc_resume(); + + // disable render control + Write32(OUT, 0x000300, Read32(OUT, 0x000300) & 0xFFFCFFFF); + + return B_OK; +} + + +static status_t +radeon_gpu_mc_setup_r700() +{ + // HDP initialization + uint32 i; + uint32 j; + for (i = 0, j = 0; i < 32; i++, j += 0x18) { + Write32(OUT, (0x2c14 + j), 0x00000000); + Write32(OUT, (0x2c18 + j), 0x00000000); + Write32(OUT, (0x2c1c + j), 0x00000000); + Write32(OUT, (0x2c20 + j), 0x00000000); + Write32(OUT, (0x2c24 + j), 0x00000000); + } + + // On r7xx read from HDP_DEBUG1 vs write HDP_REG_COHERENCY_FLUSH_CNTL + Read32(OUT, HDP_DEBUG1); + + // idle the memory controller + radeon_gpu_mc_halt(); + + uint32 idleState = radeon_gpu_mc_idlecheck(); + if (idleState > 0) { + ERROR("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n", + __func__, idleState); + //return B_ERROR; + } + + // TODO: Memory Controller AGP + Write32(OUT, R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, + gInfo->mc.vramStart >> 12); + Write32(OUT, R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, + gInfo->mc.vramEnd >> 12); + + Write32(OUT, R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); + uint32 tmp = ((gInfo->mc.vramEnd >> 24) & 0xFFFF) << 16; + tmp |= ((gInfo->mc.vramStart >> 24) & 0xFFFF); + + Write32(OUT, R600_MC_VM_FB_LOCATION, tmp); Write32(OUT, HDP_NONSURFACE_BASE, (gInfo->mc.vramStart >> 8)); Write32(OUT, HDP_NONSURFACE_INFO, (2 << 7)); Write32(OUT, HDP_NONSURFACE_SIZE, 0x3FFFFFFF); @@ -303,7 +370,7 @@ radeon_gpu_mc_init() uint64 vramBase = gInfo->shared_info->frame_buffer_phys; if ((info.chipsetFlags & CHIP_IGP) != 0) { - vramBase = Read32(OUT, R6XX_MC_VM_FB_LOCATION) & 0xFFFF; + vramBase = Read32(OUT, R600_MC_VM_FB_LOCATION) & 0xFFFF; vramBase <<= 24; } @@ -329,7 +396,9 @@ radeon_gpu_mc_setup() TRACE("%s: vramStart: 0x%" B_PRIX64 ", vramEnd: 0x%" B_PRIX64 "\n", __func__, gInfo->mc.vramStart, gInfo->mc.vramEnd); - if (info.device_chipset >= RADEON_R600) + if (info.device_chipset >= RADEON_R700) + return radeon_gpu_mc_setup_r700(); + else if (info.device_chipset >= RADEON_R600) return radeon_gpu_mc_setup_r600(); return B_ERROR; diff --git a/src/add-ons/accelerants/radeon_hd/mode.cpp b/src/add-ons/accelerants/radeon_hd/mode.cpp index 63805a08b6..5ce71dd76a 100644 --- a/src/add-ons/accelerants/radeon_hd/mode.cpp +++ b/src/add-ons/accelerants/radeon_hd/mode.cpp @@ -213,16 +213,18 @@ radeon_set_display_mode(display_mode *mode) TRACE("D2CRTC_STATUS Value: 0x%X\n", Read32(CRT, D2CRTC_STATUS)); TRACE("D1CRTC_CONTROL Value: 0x%X\n", Read32(CRT, D1CRTC_CONTROL)); TRACE("D2CRTC_CONTROL Value: 0x%X\n", Read32(CRT, D2CRTC_CONTROL)); - TRACE("D1GRPH_ENABLE Value: 0x%X\n", Read32(CRT, D1GRPH_ENABLE)); - TRACE("D2GRPH_ENABLE Value: 0x%X\n", Read32(CRT, D2GRPH_ENABLE)); - TRACE("D1SCL_ENABLE Value: 0x%X\n", Read32(CRT, D1SCL_ENABLE)); - TRACE("D2SCL_ENABLE Value: 0x%X\n", Read32(CRT, D2SCL_ENABLE)); - TRACE("RV620_DACA_ENABLE Value: 0x%X\n", Read32(CRT, RV620_DACA_ENABLE)); - TRACE("RV620_DACB_ENABLE Value: 0x%X\n", Read32(CRT, RV620_DACB_ENABLE)); + TRACE("D1GRPH_ENABLE Value: 0x%X\n", + Read32(CRT, AVIVO_D1GRPH_ENABLE)); + TRACE("D2GRPH_ENABLE Value: 0x%X\n", + Read32(CRT, AVIVO_D2GRPH_ENABLE)); + TRACE("D1SCL_ENABLE Value: 0x%X\n", + Read32(CRT, AVIVO_D1SCL_SCALER_ENABLE)); + TRACE("D2SCL_ENABLE Value: 0x%X\n", + Read32(CRT, AVIVO_D2SCL_SCALER_ENABLE)); TRACE("D1CRTC_BLANK_CONTROL Value: 0x%X\n", - Read32(CRT, D1CRTC_BLANK_CONTROL)); + Read32(CRT, AVIVO_D1CRTC_BLANK_CONTROL)); TRACE("D2CRTC_BLANK_CONTROL Value: 0x%X\n", - Read32(CRT, D2CRTC_BLANK_CONTROL)); + Read32(CRT, AVIVO_D1CRTC_BLANK_CONTROL)); return B_OK; } diff --git a/src/add-ons/accelerants/radeon_hd/pll.cpp b/src/add-ons/accelerants/radeon_hd/pll.cpp index b0abd2d0d7..95e40bbfb4 100644 --- a/src/add-ons/accelerants/radeon_hd/pll.cpp +++ b/src/add-ons/accelerants/radeon_hd/pll.cpp @@ -303,7 +303,7 @@ pll_setup_flags(pll_info *pll, uint8 crtcID) pll->flags |= PLL_PREFER_LOW_REF_DIV; - if (info.device_chipset < (RADEON_R700 | 0x70)) + if (info.device_chipset < RADEON_R700) pll->flags |= PLL_PREFER_MINM_OVER_MAXP; diff --git a/src/add-ons/kernel/drivers/graphics/radeon_hd/driver.cpp b/src/add-ons/kernel/drivers/graphics/radeon_hd/driver.cpp index 65b1c989a0..bf4f880291 100644 --- a/src/add-ons/kernel/drivers/graphics/radeon_hd/driver.cpp +++ b/src/add-ons/kernel/drivers/graphics/radeon_hd/driver.cpp @@ -122,8 +122,6 @@ const struct supported_device { // From here on AMD no longer used numeric identifiers - // TODO: These don't work yet, no video. (maybe FB issue?) - # if 0 // R1000 series (HD54xx - HD63xx) // Codename: Evergreen // Cedar @@ -199,7 +197,6 @@ const struct supported_device { {0x671F, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD 6900"}, // Antilles {0x671d, 5, 0, RADEON_R2000 | 0x40, CHIP_STD, "Radeon HD 6990"} - #endif // R3000 series (HD74xx - HD79xx) // Codename: Southern Islands diff --git a/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp b/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp index c4f44cdeb6..efc2c2bc86 100644 --- a/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp +++ b/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp @@ -485,13 +485,13 @@ radeon_hd_init(radeon_info &info) // *** Populate frame buffer information if (info.shared_info->device_chipset >= RADEON_R1000) { - // R800+ has memory stored in MB + // Evergreen+ has memory stored in MB info.shared_info->graphics_memory_size - = read32(info.registers + R6XX_CONFIG_MEMSIZE) * 1024; + = read32(info.registers + CONFIG_MEMSIZE) * 1024; } else { // R600-R700 has memory stored in bytes info.shared_info->graphics_memory_size - = read32(info.registers + R6XX_CONFIG_MEMSIZE) / 1024; + = read32(info.registers + CONFIG_MEMSIZE) / 1024; } uint32 barSize = info.pci->u.h0.base_register_sizes[RHD_FB_BAR] / 1024;