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intel_extreme: updated PLL restricts, updated set- and proposemode. Requested modes are now set more precise.
This commit is contained in:
Rudolf Cornelissen
parent
6846668fd7
commit
3a9bb1e729
@ -273,42 +273,21 @@ intel_propose_display_mode(display_mode* target, const display_mode* low,
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{
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CALLED();
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// first search for the specified mode in the list, if no mode is found
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// try to fix the target mode in sanitize_display_mode
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// TODO: Only sanitize_display_mode should be used. However, at the moment
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// the mode constraints are not optimal and do not work for all
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// configurations.
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uint32 VirtualWidth = target->virtual_width;
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uint32 VirtualHeight = target->virtual_height;
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float RefreshRate = (float)target->timing.pixel_clock /
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(target->timing.h_total * target->timing.v_total);
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display_mode mode = *target;
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for (uint32 i = 0; i < gInfo->shared_info->mode_count; i++) {
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display_mode *mode = &gInfo->mode_list[i];
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// TODO: improve this, ie. adapt pixel clock to allowed values!!!
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if (target->timing.h_display != mode->timing.h_display
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|| target->timing.v_display != mode->timing.v_display
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|| target->space != mode->space) {
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continue;
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}
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*target = *mode;
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// retain requested virtual size
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target->virtual_width = VirtualWidth;
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target->virtual_height = VirtualHeight;
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// retain requested refreshrate
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target->timing.pixel_clock =
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target->timing.h_total * target->timing.v_total * RefreshRate;
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// (most) modeflags are outputs from us (the driver). So we should
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// set them depending on the mode and the current hardware config
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target->flags |= B_SCROLL;
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return B_OK;
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if (sanitize_display_mode(*target)) {
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TRACE("Video mode was adjusted by sanitize_display_mode\n");
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TRACE("Initial mode: Hd %d Hs %d He %d Ht %d Vd %d Vs %d Ve %d Vt %d\n",
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mode.timing.h_display, mode.timing.h_sync_start,
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mode.timing.h_sync_end, mode.timing.h_total,
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mode.timing.v_display, mode.timing.v_sync_start,
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mode.timing.v_sync_end, mode.timing.v_total);
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TRACE("Sanitized: Hd %d Hs %d He %d Ht %d Vd %d Vs %d Ve %d Vt %d\n",
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target->timing.h_display, target->timing.h_sync_start,
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target->timing.h_sync_end, target->timing.h_total,
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target->timing.v_display, target->timing.v_sync_start,
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target->timing.v_sync_end, target->timing.v_total);
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}
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sanitize_display_mode(*target);
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// (most) modeflags are outputs from us (the driver). So we should
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// set them depending on the mode and the current hardware config
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target->flags |= B_SCROLL;
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@ -329,19 +308,6 @@ intel_set_display_mode(display_mode* mode)
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display_mode target = *mode;
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if (sanitize_display_mode(target)) { //should be in proposemode..
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TRACE("Video mode was adjusted by sanitize_display_mode\n");
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TRACE("Initial mode: Hd %d Hs %d He %d Ht %d Vd %d Vs %d Ve %d Vt %d\n",
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mode->timing.h_display, mode->timing.h_sync_start,
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mode->timing.h_sync_end, mode->timing.h_total,
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mode->timing.v_display, mode->timing.v_sync_start,
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mode->timing.v_sync_end, mode->timing.v_total);
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TRACE("Sanitized: Hd %d Hs %d He %d Ht %d Vd %d Vs %d Ve %d Vt %d\n",
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target.timing.h_display, target.timing.h_sync_start,
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target.timing.h_sync_end, target.timing.h_total,
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target.timing.v_display, target.timing.v_sync_start,
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target.timing.v_sync_end, target.timing.v_total);
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}
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if (intel_propose_display_mode(&target, &target, &target) != B_OK)
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return B_BAD_VALUE;
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@ -39,89 +39,86 @@
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#define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__)
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// PLL limits, taken from programming manual when available, and from Linux KMS
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// drivers otherwise. However, note that we use the values of N+2, M1+2 and
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// M2+2 here, the - 2 being applied when we write the values to the registers.
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// PLL limits, taken from i915 DRM driver. However, note that we use the values of
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// N+2, M1+2 and M2+2 here, the - 2 being applied when we write the values to the registers.
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static pll_limits kLimits85x = {
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// p, p1, p2, n, m, m1, m2
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{ 4, 2, 2, 5, 96, 20, 8},
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{ 4, 2, 2, 4, 96, 20, 8},
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{128, 33, 4, 18, 140, 28, 18},
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165000, 930000, 1400000
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165000, 908000, 1512000
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};
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// TODO according to the docs, the limits for 9xx anf G45 should be the same.
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// For Iron Lake, a new set of timings is introduced along with the FDI system,
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// and carried on to later cards with just one further change (to the P2 cutoff
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// frequency) in Sandy Bridge.
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//
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// So, it makes no sense to have separate limits and algorithm for 9xx and G45.
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static pll_limits kLimits9xxSdvo = {
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// p, p1, p2, n, m, m1, m2
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{ 5, 1, 5, 5, 70, 12, 7}, // min
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{ 80, 8, 10, 10, 120, 22, 11}, // max
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{ 5, 1, 5, 3, 70, 10, 5}, // min
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{ 80, 8, 10, 8, 120, 20, 9}, // max
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200000, 1400000, 2800000
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};
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static pll_limits kLimits9xxLvds = {
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// p, p1, p2, n, m, m1, m2
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{ 7, 1, 7, 1, 70, 8, 3}, // min
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{ 98, 8, 14, 6, 120, 18, 7}, // max
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{ 7, 1, 7, 3, 70, 10, 5}, // min
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{ 98, 8, 14, 8, 120, 20, 9}, // max
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112000, 1400000, 2800000
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};
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// Limits for G45 cards taken from g45_vlo3_register_0_0_0.pdf, page 46
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// Note that n here is actually n+2, but m1 and m2 are as in the datasheet.
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// Limits for G45 cards taken from i915 DRM driver, mixed with old setup
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// plus tests to accomodate lower resolutions with still correct refresh.
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// Note that n here is actually n+2, same applies to m1 and m2.
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static pll_limits kLimitsG4xSdvo = {
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// p, p1, p2, n, m, m1, m2
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{ 5, 1, 5, 5, 70, 12, 7}, // min
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{ 80, 8, 10, 10, 120, 22, 11}, // max
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270000, 1400000, 2800000
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{ 10, 1, 10, 3, 104, 19, 7}, // min
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{ 80, 8, 10, 8, 138, 25, 13}, // max
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270000, 1750000, 3500000
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};
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#if 0
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static pll_limits kLimitsG4xHdmi = {
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// p, p1, p2, n, m, m1, m2
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{ 5, 1, 5, 5, 70, 12, 7}, // min
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{ 80, 8, 10, 10, 120, 22, 11}, // max
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165000, 1400000, 2800000
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{ 5, 1, 5, 3, 104, 18, 7}, // min
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{ 80, 8, 10, 8, 138, 25, 13}, // max
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165000, 1750000, 3500000
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};
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#endif
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static pll_limits kLimitsG4xLvdsSingle = {
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// p, p1, p2, n, m, m1, m2
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{ 7, 1, 14, 5, 70, 12, 7}, // min
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{ 98, 8, 14, 10, 120, 22, 11}, // max
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0, 1400000, 2800000
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{ 28, 2, 14, 3, 104, 19, 7}, // min
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{112, 8, 14, 8, 138, 25, 13}, // max
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0, 1750000, 3500000
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};
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static pll_limits kLimitsG4xLvdsDual = {
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// p, p1, p2, n, m, m1, m2
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{ 14, 2, 7, 5, 70, 12, 7}, // min
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{ 42, 6, 7, 10, 120, 22, 11}, // max
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0, 1400000, 2800000
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{ 14, 2, 7, 3, 104, 19, 7}, // min
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{ 42, 6, 7, 8, 138, 25, 13}, // max
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0, 1750000, 3500000
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};
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static pll_limits kLimitsIlkDac = {
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// p, p1, p2, n, m, m1, m2
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{ 5, 1, 5, 3, 79, 14, 7}, // min
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{ 80, 8, 10, 8, 118, 24, 11}, // max
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{ 80, 8, 10, 7, 127, 24, 11}, // max
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225000, 1760000, 3510000
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};
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static pll_limits kLimitsIlkLvdsSingle = {
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// p, p1, p2, n, m, m1, m2
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{ 28, 2, 14, 3, 79, 14, 7}, // min
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{112, 8, 14, 8, 118, 24, 11}, // max
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{112, 8, 14, 5, 118, 24, 11}, // max
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225000, 1760000, 3510000
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};
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static pll_limits kLimitsIlkLvdsDual = {
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// p, p1, p2, n, m, m1, m2
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{ 14, 2, 7, 3, 79, 14, 7}, // min
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{ 56, 8, 7, 8, 127, 24, 11}, // max
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{ 56, 8, 7, 5, 127, 24, 11}, // max
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225000, 1760000, 3510000
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};
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@ -129,14 +126,14 @@ static pll_limits kLimitsIlkLvdsDual = {
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static pll_limits kLimitsIlkLvdsSingle100 = {
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// p, p1, p2, n, m, m1, m2
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{ 28, 2, 14, 3, 79, 14, 7}, // min
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{112, 8, 14, 8, 126, 24, 11}, // max
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{112, 8, 14, 4, 126, 24, 11}, // max
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225000, 1760000, 3510000
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};
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static pll_limits kLimitsIlkLvdsDual100 = {
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// p, p1, p2, n, m, m1, m2
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{ 14, 2, 7, 3, 79, 14, 7}, // min
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{ 42, 6, 7, 8, 126, 24, 11}, // max
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{ 42, 6, 7, 5, 126, 24, 11}, // max
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225000, 1760000, 3510000
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};
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@ -345,8 +342,8 @@ compute_dpll_g4x(display_mode* current, pll_divisors* divisors, bool isLVDS)
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continue;
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float error = fabs(requestedPixelClock
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- ((referenceClock * divisors->m) / divisors->n)
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/ divisors->p);
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- (referenceClock * divisors->m)
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/ (divisors->n * divisors->p));
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if (error < best) {
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best = error;
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bestDivisors = *divisors;
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@ -360,7 +357,7 @@ compute_dpll_g4x(display_mode* current, pll_divisors* divisors, bool isLVDS)
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}
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*divisors = bestDivisors;
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TRACE("%s: best MHz: %g (error: %g)\n", __func__,
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((referenceClock * divisors->m) / divisors->n) / divisors->p,
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(referenceClock * divisors->m) / (divisors->n * divisors->p),
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best);
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}
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@ -423,8 +420,8 @@ compute_dpll_9xx(display_mode* current, pll_divisors* divisors, bool isLVDS)
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continue;
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float error = fabs(requestedPixelClock
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- ((referenceClock * divisors->m) / divisors->n)
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/ divisors->p);
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- (referenceClock * divisors->m)
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/ (divisors->n * divisors->p));
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if (error < best) {
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best = error;
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bestDivisors = *divisors;
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@ -443,7 +440,7 @@ compute_dpll_9xx(display_mode* current, pll_divisors* divisors, bool isLVDS)
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debugger("No valid PLL configuration found");
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else {
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TRACE("%s: best MHz: %g (error: %g)\n", __func__,
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((referenceClock * divisors->m) / divisors->n) / divisors->p,
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(referenceClock * divisors->m) / (divisors->n * divisors->p),
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best);
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}
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}
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