mirror of
https://review.haiku-os.org/haiku
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vmx: Introduce VMXNET3 Network Driver from FreeBSD 14.1
Tested with VMWare Workstation Pro 17.6.0 with Haiku x86_64 hrev58201. To test, had to manually open the .vmx file associated with the VM and added the line: ethernet0.virtualDev = "vmxnet3" Change-Id: Ic76dcc61583707345bee46624814a38f66eb4f9f Reviewed-on: https://review.haiku-os.org/c/haiku/+/8438 Reviewed-by: waddlesplash <waddlesplash@gmail.com>
This commit is contained in:
CodeforEvolution
waddlesplash
parent
0059775c1d
commit
48d27198d0
@ -332,6 +332,7 @@ SYSTEM_ADD_ONS_DRIVERS_NET = [ FFilterByBuildFeatures
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sis900
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syskonnect
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via_rhine
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vmx
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vt612x
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}@ # x86,x86_64,riscv64
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@ -33,6 +33,7 @@ HaikuSubInclude sis19x ;
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HaikuSubInclude sis900 ;
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HaikuSubInclude syskonnect ;
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HaikuSubInclude via_rhine ;
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HaikuSubInclude vmx ;
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HaikuSubInclude vt612x ;
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# OpenBSD drivers
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18
src/add-ons/kernel/drivers/network/ether/vmx/Jamfile
Normal file
18
src/add-ons/kernel/drivers/network/ether/vmx/Jamfile
Normal file
@ -0,0 +1,18 @@
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SubDir HAIKU_TOP src add-ons kernel drivers network ether vmx ;
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UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_iflib compat ] : true ;
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UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
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UsePrivateHeaders net system ;
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UsePrivateKernelHeaders ;
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UseHeaders [ FDirName $(SUBDIR) ] : true ;
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SEARCH_SOURCE += [ FDirName $(SUBDIR) dev vmxnet3 ] ;
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SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 _XOPEN_SOURCE ] ;
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KernelAddon vmx :
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glue.c
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if_vmx.c
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: freebsd_iflib.a libfreebsd_network.a
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;
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2558
src/add-ons/kernel/drivers/network/ether/vmx/dev/vmxnet3/if_vmx.c
Normal file
2558
src/add-ons/kernel/drivers/network/ether/vmx/dev/vmxnet3/if_vmx.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,341 @@
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/*-
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* Copyright (c) 2013 Tsubai Masanari
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $OpenBSD: src/sys/dev/pci/if_vmxreg.h,v 1.2 2013/06/12 01:07:33 uebayasi Exp $
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*/
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#ifndef _IF_VMXREG_H
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#define _IF_VMXREG_H
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struct UPT1_TxStats {
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uint64_t TSO_packets;
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uint64_t TSO_bytes;
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uint64_t ucast_packets;
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uint64_t ucast_bytes;
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uint64_t mcast_packets;
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uint64_t mcast_bytes;
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uint64_t bcast_packets;
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uint64_t bcast_bytes;
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uint64_t error;
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uint64_t discard;
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} __packed;
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struct UPT1_RxStats {
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uint64_t LRO_packets;
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uint64_t LRO_bytes;
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uint64_t ucast_packets;
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uint64_t ucast_bytes;
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uint64_t mcast_packets;
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uint64_t mcast_bytes;
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uint64_t bcast_packets;
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uint64_t bcast_bytes;
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uint64_t nobuffer;
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uint64_t error;
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} __packed;
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/* Interrupt moderation levels */
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#define UPT1_IMOD_NONE 0 /* No moderation */
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#define UPT1_IMOD_HIGHEST 7 /* Least interrupts */
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#define UPT1_IMOD_ADAPTIVE 8 /* Adaptive interrupt moderation */
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/* Hardware features */
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#define UPT1_F_CSUM 0x0001 /* Rx checksum verification */
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#define UPT1_F_RSS 0x0002 /* Receive side scaling */
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#define UPT1_F_VLAN 0x0004 /* VLAN tag stripping */
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#define UPT1_F_LRO 0x0008 /* Large receive offloading */
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#define VMXNET3_BAR0_IMASK(irq) (0x000 + (irq) * 8) /* Interrupt mask */
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#define VMXNET3_BAR0_TXH(q) (0x600 + (q) * 8) /* Tx head */
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#define VMXNET3_BAR0_RXH1(q) (0x800 + (q) * 8) /* Ring1 Rx head */
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#define VMXNET3_BAR0_RXH2(q) (0xA00 + (q) * 8) /* Ring2 Rx head */
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#define VMXNET3_BAR1_VRRS 0x000 /* VMXNET3 revision report selection */
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#define VMXNET3_BAR1_UVRS 0x008 /* UPT version report selection */
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#define VMXNET3_BAR1_DSL 0x010 /* Driver shared address low */
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#define VMXNET3_BAR1_DSH 0x018 /* Driver shared address high */
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#define VMXNET3_BAR1_CMD 0x020 /* Command */
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#define VMXNET3_BAR1_MACL 0x028 /* MAC address low */
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#define VMXNET3_BAR1_MACH 0x030 /* MAC address high */
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#define VMXNET3_BAR1_INTR 0x038 /* Interrupt status */
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#define VMXNET3_BAR1_EVENT 0x040 /* Event status */
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#define VMXNET3_CMD_ENABLE 0xCAFE0000 /* Enable VMXNET3 */
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#define VMXNET3_CMD_DISABLE 0xCAFE0001 /* Disable VMXNET3 */
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#define VMXNET3_CMD_RESET 0xCAFE0002 /* Reset device */
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#define VMXNET3_CMD_SET_RXMODE 0xCAFE0003 /* Set interface flags */
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#define VMXNET3_CMD_SET_FILTER 0xCAFE0004 /* Set address filter */
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#define VMXNET3_CMD_VLAN_FILTER 0xCAFE0005 /* Set VLAN filter */
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#define VMXNET3_CMD_GET_STATUS 0xF00D0000 /* Get queue errors */
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#define VMXNET3_CMD_GET_STATS 0xF00D0001 /* Get queue statistics */
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#define VMXNET3_CMD_GET_LINK 0xF00D0002 /* Get link status */
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#define VMXNET3_CMD_GET_MACL 0xF00D0003 /* Get MAC address low */
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#define VMXNET3_CMD_GET_MACH 0xF00D0004 /* Get MAC address high */
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#define VMXNET3_CMD_GET_INTRCFG 0xF00D0008 /* Get interrupt config */
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#define VMXNET3_DMADESC_ALIGN 128
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#define VMXNET3_INIT_GEN 1
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struct vmxnet3_txdesc {
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uint64_t addr;
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uint32_t len:14;
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uint32_t gen:1; /* Generation */
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uint32_t pad1:1;
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uint32_t dtype:1; /* Descriptor type */
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uint32_t pad2:1;
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uint32_t offload_pos:14; /* Offloading position */
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uint32_t hlen:10; /* Header len */
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uint32_t offload_mode:2; /* Offloading mode */
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uint32_t eop:1; /* End of packet */
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uint32_t compreq:1; /* Completion request */
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uint32_t pad3:1;
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uint32_t vtag_mode:1; /* VLAN tag insertion mode */
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uint32_t vtag:16; /* VLAN tag */
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} __packed;
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/* Offloading modes */
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#define VMXNET3_OM_NONE 0
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#define VMXNET3_OM_CSUM 2
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#define VMXNET3_OM_TSO 3
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struct vmxnet3_txcompdesc {
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uint32_t eop_idx:12; /* EOP index in Tx ring */
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uint32_t pad1:20;
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uint32_t pad2:32;
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uint32_t pad3:32;
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uint32_t rsvd:24;
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uint32_t type:7;
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uint32_t gen:1;
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} __packed;
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struct vmxnet3_rxdesc {
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uint64_t addr;
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uint32_t len:14;
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uint32_t btype:1; /* Buffer type */
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uint32_t dtype:1; /* Descriptor type */
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uint32_t rsvd:15;
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uint32_t gen:1;
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uint32_t pad1:32;
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} __packed;
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/* Buffer types */
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#define VMXNET3_BTYPE_HEAD 0 /* Head only */
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#define VMXNET3_BTYPE_BODY 1 /* Body only */
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struct vmxnet3_rxcompdesc {
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uint32_t rxd_idx:12; /* Rx descriptor index */
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uint32_t pad1:2;
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uint32_t eop:1; /* End of packet */
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uint32_t sop:1; /* Start of packet */
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uint32_t qid:10;
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uint32_t rss_type:4;
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uint32_t no_csum:1; /* No checksum calculated */
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uint32_t pad2:1;
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uint32_t rss_hash:32; /* RSS hash value */
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uint32_t len:14;
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uint32_t error:1;
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uint32_t vlan:1; /* 802.1Q VLAN frame */
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uint32_t vtag:16; /* VLAN tag */
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uint32_t csum:16;
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uint32_t csum_ok:1; /* TCP/UDP checksum ok */
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uint32_t udp:1;
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uint32_t tcp:1;
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uint32_t ipcsum_ok:1; /* IP checksum OK */
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uint32_t ipv6:1;
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uint32_t ipv4:1;
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uint32_t fragment:1; /* IP fragment */
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uint32_t fcs:1; /* Frame CRC correct */
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uint32_t type:7;
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uint32_t gen:1;
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} __packed;
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#define VMXNET3_RCD_RSS_TYPE_NONE 0
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#define VMXNET3_RCD_RSS_TYPE_IPV4 1
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#define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2
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#define VMXNET3_RCD_RSS_TYPE_IPV6 3
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#define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4
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#define VMXNET3_REV1_MAGIC 0XBABEFEE1
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#define VMXNET3_GOS_UNKNOWN 0x00
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#define VMXNET3_GOS_LINUX 0x04
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#define VMXNET3_GOS_WINDOWS 0x08
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#define VMXNET3_GOS_SOLARIS 0x0C
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#define VMXNET3_GOS_FREEBSD 0x10
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#define VMXNET3_GOS_PXE 0x14
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#define VMXNET3_GOS_32BIT 0x01
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#define VMXNET3_GOS_64BIT 0x02
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#define VMXNET3_MAX_TX_QUEUES 8
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#define VMXNET3_MAX_RX_QUEUES 16
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#define VMXNET3_MAX_INTRS \
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(VMXNET3_MAX_TX_QUEUES + VMXNET3_MAX_RX_QUEUES + 1)
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#define VMXNET3_ICTRL_DISABLE_ALL 0x01
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#define VMXNET3_RXMODE_UCAST 0x01
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#define VMXNET3_RXMODE_MCAST 0x02
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#define VMXNET3_RXMODE_BCAST 0x04
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#define VMXNET3_RXMODE_ALLMULTI 0x08
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#define VMXNET3_RXMODE_PROMISC 0x10
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#define VMXNET3_EVENT_RQERROR 0x01
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#define VMXNET3_EVENT_TQERROR 0x02
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#define VMXNET3_EVENT_LINK 0x04
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#define VMXNET3_EVENT_DIC 0x08
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#define VMXNET3_EVENT_DEBUG 0x10
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#define VMXNET3_MIN_MTU 60
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#define VMXNET3_MAX_MTU 9000
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/* Interrupt mask mode. */
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#define VMXNET3_IMM_AUTO 0x00
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#define VMXNET3_IMM_ACTIVE 0x01
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#define VMXNET3_IMM_LAZY 0x02
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/* Interrupt type. */
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#define VMXNET3_IT_AUTO 0x00
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#define VMXNET3_IT_LEGACY 0x01
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#define VMXNET3_IT_MSI 0x02
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#define VMXNET3_IT_MSIX 0x03
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struct vmxnet3_driver_shared {
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uint32_t magic;
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uint32_t pad1;
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/* Misc. control */
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uint32_t version; /* Driver version */
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uint32_t guest; /* Guest OS */
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uint32_t vmxnet3_revision; /* Supported VMXNET3 revision */
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uint32_t upt_version; /* Supported UPT version */
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uint64_t upt_features;
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uint64_t driver_data;
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uint64_t queue_shared;
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uint32_t driver_data_len;
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uint32_t queue_shared_len;
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uint32_t mtu;
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uint16_t nrxsg_max;
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uint8_t ntxqueue;
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uint8_t nrxqueue;
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uint32_t reserved1[4];
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/* Interrupt control */
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uint8_t automask;
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uint8_t nintr;
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uint8_t evintr;
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uint8_t modlevel[VMXNET3_MAX_INTRS];
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uint32_t ictrl;
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uint32_t reserved2[2];
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/* Receive filter parameters */
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uint32_t rxmode;
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uint16_t mcast_tablelen;
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uint16_t pad2;
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uint64_t mcast_table;
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uint32_t vlan_filter[4096 / 32];
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struct {
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uint32_t version;
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uint32_t len;
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uint64_t paddr;
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} rss, pm, plugin;
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uint32_t event;
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uint32_t reserved3[5];
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} __packed;
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struct vmxnet3_txq_shared {
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/* Control */
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uint32_t npending;
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uint32_t intr_threshold;
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uint64_t reserved1;
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/* Config */
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uint64_t cmd_ring;
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uint64_t data_ring;
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uint64_t comp_ring;
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uint64_t driver_data;
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uint64_t reserved2;
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uint32_t cmd_ring_len;
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uint32_t data_ring_len;
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uint32_t comp_ring_len;
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uint32_t driver_data_len;
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uint8_t intr_idx;
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uint8_t pad1[7];
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/* Queue status */
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uint8_t stopped;
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uint8_t pad2[3];
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uint32_t error;
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struct UPT1_TxStats stats;
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uint8_t pad3[88];
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} __packed;
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struct vmxnet3_rxq_shared {
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uint8_t update_rxhead;
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uint8_t pad1[7];
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uint64_t reserved1;
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uint64_t cmd_ring[2];
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uint64_t comp_ring;
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uint64_t driver_data;
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uint64_t reserved2;
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uint32_t cmd_ring_len[2];
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uint32_t comp_ring_len;
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uint32_t driver_data_len;
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uint8_t intr_idx;
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uint8_t pad2[7];
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uint8_t stopped;
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uint8_t pad3[3];
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uint32_t error;
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struct UPT1_RxStats stats;
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uint8_t pad4[88];
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} __packed;
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#define UPT1_RSS_HASH_TYPE_NONE 0x00
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#define UPT1_RSS_HASH_TYPE_IPV4 0x01
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#define UPT1_RSS_HASH_TYPE_TCP_IPV4 0x02
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#define UPT1_RSS_HASH_TYPE_IPV6 0x04
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#define UPT1_RSS_HASH_TYPE_TCP_IPV6 0x08
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#define UPT1_RSS_HASH_FUNC_NONE 0x00
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#define UPT1_RSS_HASH_FUNC_TOEPLITZ 0x01
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#define UPT1_RSS_MAX_KEY_SIZE 40
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#define UPT1_RSS_MAX_IND_TABLE_SIZE 128
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struct vmxnet3_rss_shared {
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uint16_t hash_type;
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uint16_t hash_func;
|
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uint16_t hash_key_size;
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uint16_t ind_table_size;
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uint8_t hash_key[UPT1_RSS_MAX_KEY_SIZE];
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uint8_t ind_table[UPT1_RSS_MAX_IND_TABLE_SIZE];
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} __packed;
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#endif /* _IF_VMXREG_H */
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@ -0,0 +1,198 @@
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/*-
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* Copyright (c) 2013 Tsubai Masanari
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* Copyright (c) 2013 Bryan Venteicher <bryanv@FreeBSD.org>
|
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* Copyright (c) 2018 Patrick Kelsey
|
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*
|
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* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
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#ifndef _IF_VMXVAR_H
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#define _IF_VMXVAR_H
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struct vmxnet3_softc;
|
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|
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/*
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* The number of Rx/Tx queues this driver prefers.
|
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*/
|
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#define VMXNET3_DEF_RX_QUEUES 8
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#define VMXNET3_DEF_TX_QUEUES 8
|
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/*
|
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* The number of Rx rings in each Rx queue.
|
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*/
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#define VMXNET3_RXRINGS_PERQ 2
|
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|
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/*
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* The number of descriptors in each Rx/Tx ring.
|
||||
*/
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#define VMXNET3_DEF_TX_NDESC 512
|
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#define VMXNET3_MAX_TX_NDESC 4096
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#define VMXNET3_MIN_TX_NDESC 32
|
||||
#define VMXNET3_MASK_TX_NDESC 0x1F
|
||||
#define VMXNET3_DEF_RX_NDESC 512
|
||||
#define VMXNET3_MAX_RX_NDESC 2048
|
||||
#define VMXNET3_MIN_RX_NDESC 32
|
||||
#define VMXNET3_MASK_RX_NDESC 0x1F
|
||||
|
||||
#define VMXNET3_MAX_TX_NCOMPDESC VMXNET3_MAX_TX_NDESC
|
||||
#define VMXNET3_MAX_RX_NCOMPDESC \
|
||||
(VMXNET3_MAX_RX_NDESC * VMXNET3_RXRINGS_PERQ)
|
||||
|
||||
struct vmxnet3_txring {
|
||||
u_int vxtxr_next;
|
||||
u_int vxtxr_ndesc;
|
||||
int vxtxr_gen;
|
||||
struct vmxnet3_txdesc *vxtxr_txd;
|
||||
bus_addr_t vxtxr_paddr;
|
||||
};
|
||||
|
||||
struct vmxnet3_rxring {
|
||||
struct vmxnet3_rxdesc *vxrxr_rxd;
|
||||
u_int vxrxr_ndesc;
|
||||
int vxrxr_gen;
|
||||
bus_addr_t vxrxr_paddr;
|
||||
uint64_t vxrxr_desc_skips;
|
||||
uint16_t vxrxr_refill_start;
|
||||
};
|
||||
|
||||
struct vmxnet3_comp_ring {
|
||||
union {
|
||||
struct vmxnet3_txcompdesc *txcd;
|
||||
struct vmxnet3_rxcompdesc *rxcd;
|
||||
} vxcr_u;
|
||||
/*
|
||||
* vxcr_next is used on the transmit side to track the next index to
|
||||
* begin cleaning at. It is not used on the receive side.
|
||||
*/
|
||||
u_int vxcr_next;
|
||||
u_int vxcr_ndesc;
|
||||
int vxcr_gen;
|
||||
bus_addr_t vxcr_paddr;
|
||||
uint64_t vxcr_zero_length;
|
||||
uint64_t vcxr_zero_length_frag;
|
||||
uint64_t vxcr_pkt_errors;
|
||||
};
|
||||
|
||||
struct vmxnet3_txqueue {
|
||||
struct vmxnet3_softc *vxtxq_sc;
|
||||
int vxtxq_id;
|
||||
int vxtxq_last_flush;
|
||||
int vxtxq_intr_idx;
|
||||
struct vmxnet3_txring vxtxq_cmd_ring;
|
||||
struct vmxnet3_comp_ring vxtxq_comp_ring;
|
||||
struct vmxnet3_txq_shared *vxtxq_ts;
|
||||
struct sysctl_oid_list *vxtxq_sysctl;
|
||||
char vxtxq_name[16];
|
||||
} __aligned(CACHE_LINE_SIZE);
|
||||
|
||||
struct vmxnet3_rxqueue {
|
||||
struct vmxnet3_softc *vxrxq_sc;
|
||||
int vxrxq_id;
|
||||
int vxrxq_intr_idx;
|
||||
struct if_irq vxrxq_irq;
|
||||
struct vmxnet3_rxring vxrxq_cmd_ring[VMXNET3_RXRINGS_PERQ];
|
||||
struct vmxnet3_comp_ring vxrxq_comp_ring;
|
||||
struct vmxnet3_rxq_shared *vxrxq_rs;
|
||||
struct sysctl_oid_list *vxrxq_sysctl;
|
||||
char vxrxq_name[16];
|
||||
} __aligned(CACHE_LINE_SIZE);
|
||||
|
||||
struct vmxnet3_softc {
|
||||
device_t vmx_dev;
|
||||
if_ctx_t vmx_ctx;
|
||||
if_shared_ctx_t vmx_sctx;
|
||||
if_softc_ctx_t vmx_scctx;
|
||||
if_t vmx_ifp;
|
||||
struct vmxnet3_driver_shared *vmx_ds;
|
||||
uint32_t vmx_flags;
|
||||
#define VMXNET3_FLAG_RSS 0x0002
|
||||
#define VMXNET3_FLAG_SOFT_RSS 0x0004 /* Software RSS is enabled with
|
||||
compatible algorithm. */
|
||||
|
||||
struct vmxnet3_rxqueue *vmx_rxq;
|
||||
struct vmxnet3_txqueue *vmx_txq;
|
||||
|
||||
struct resource *vmx_res0;
|
||||
bus_space_tag_t vmx_iot0;
|
||||
bus_space_handle_t vmx_ioh0;
|
||||
struct resource *vmx_res1;
|
||||
bus_space_tag_t vmx_iot1;
|
||||
bus_space_handle_t vmx_ioh1;
|
||||
|
||||
int vmx_link_active;
|
||||
|
||||
int vmx_intr_mask_mode;
|
||||
int vmx_event_intr_idx;
|
||||
struct if_irq vmx_event_intr_irq;
|
||||
|
||||
uint8_t *vmx_mcast;
|
||||
struct vmxnet3_rss_shared *vmx_rss;
|
||||
struct iflib_dma_info vmx_ds_dma;
|
||||
struct iflib_dma_info vmx_qs_dma;
|
||||
struct iflib_dma_info vmx_mcast_dma;
|
||||
struct iflib_dma_info vmx_rss_dma;
|
||||
struct ifmedia *vmx_media;
|
||||
uint32_t vmx_vlan_filter[4096/32];
|
||||
uint8_t vmx_lladdr[ETHER_ADDR_LEN];
|
||||
};
|
||||
|
||||
/*
|
||||
* Our driver version we report to the hypervisor; we just keep
|
||||
* this value constant.
|
||||
*/
|
||||
#define VMXNET3_DRIVER_VERSION 0x00010000
|
||||
|
||||
/*
|
||||
* Max descriptors per Tx packet. We must limit the size of the
|
||||
* any TSO packets based on the number of segments.
|
||||
*/
|
||||
#define VMXNET3_TX_MAXSEGS 32 /* 64K @ 2K segment size */
|
||||
#define VMXNET3_TX_MAXSIZE (VMXNET3_TX_MAXSEGS * MCLBYTES)
|
||||
#define VMXNET3_TSO_MAXSIZE (VMXNET3_TX_MAXSIZE - ETHER_VLAN_ENCAP_LEN)
|
||||
|
||||
/*
|
||||
* Maximum supported Tx segment size. The length field in the
|
||||
* Tx descriptor is 14 bits.
|
||||
*
|
||||
* XXX It's possible a descriptor length field of 0 means 2^14, but this
|
||||
* isn't confirmed, so limit to 2^14 - 1 for now.
|
||||
*/
|
||||
#define VMXNET3_TX_MAXSEGSIZE ((1 << 14) - 1)
|
||||
|
||||
/*
|
||||
* Maximum supported Rx segment size. The length field in the
|
||||
* Rx descriptor is 14 bits.
|
||||
*
|
||||
* The reference drivers skip zero-length descriptors, which seems to be a
|
||||
* strong indication that on the receive side, a descriptor length field of
|
||||
* zero does not mean 2^14.
|
||||
*/
|
||||
#define VMXNET3_RX_MAXSEGSIZE ((1 << 14) - 1)
|
||||
|
||||
/*
|
||||
* Predetermined size of the multicast MACs filter table. If the
|
||||
* number of multicast addresses exceeds this size, then the
|
||||
* ALL_MULTI mode is use instead.
|
||||
*/
|
||||
#define VMXNET3_MULTICAST_MAX 32
|
||||
|
||||
/*
|
||||
* IP protocols that we can perform Tx checksum offloading of.
|
||||
*/
|
||||
#define VMXNET3_CSUM_OFFLOAD (CSUM_TCP | CSUM_UDP)
|
||||
#define VMXNET3_CSUM_OFFLOAD_IPV6 (CSUM_TCP_IPV6 | CSUM_UDP_IPV6)
|
||||
|
||||
#define VMXNET3_CSUM_ALL_OFFLOAD \
|
||||
(VMXNET3_CSUM_OFFLOAD | VMXNET3_CSUM_OFFLOAD_IPV6 | CSUM_TSO)
|
||||
|
||||
#endif /* _IF_VMXVAR_H */
|
||||
26
src/add-ons/kernel/drivers/network/ether/vmx/glue.c
Normal file
26
src/add-ons/kernel/drivers/network/ether/vmx/glue.c
Normal file
@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright 2024, Jacob Secunda <secundaja@gmail.com>
|
||||
* All rights reserved. Distributed under the terms of the MIT license.
|
||||
*/
|
||||
|
||||
|
||||
#include <sys/bus.h>
|
||||
|
||||
extern driver_t* DRIVER_MODULE_NAME(vmx, pci);
|
||||
|
||||
HAIKU_FBSD_DRIVERS_GLUE(vmx);
|
||||
HAIKU_DRIVER_REQUIREMENTS(0);
|
||||
NO_HAIKU_FBSD_MII_DRIVER();
|
||||
NO_HAIKU_CHECK_DISABLE_INTERRUPTS();
|
||||
NO_HAIKU_REENABLE_INTERRUPTS();
|
||||
|
||||
|
||||
status_t
|
||||
__haiku_handle_fbsd_drivers_list(status_t (*handler)(driver_t *[], driver_t *[]))
|
||||
{
|
||||
driver_t *drivers[] = {
|
||||
DRIVER_MODULE_NAME(vmx, pci),
|
||||
NULL
|
||||
};
|
||||
return (*handler)(drivers, NULL);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user