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https://review.haiku-os.org/haiku
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Intel_extreme: fixed hrev55115 regression and added FDI data/link M/N programming.
This commit is contained in:
Rudolf Cornelissen
parent
1a5fe94b7a
commit
aca9888e37
@ -727,10 +727,13 @@ struct intel_free_graphics_memory {
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#define INTEL_PIPE_DITHER_TYPE_ST2 (2 << 2)
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#define INTEL_PIPE_DITHER_TYPE_TEMP (3 << 2)
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#define INTEL_PIPE_DITHER_EN (1 << 4)
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#define INTEL_PIPE_8BPC (0 << 5)
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#define INTEL_PIPE_10BPC (1 << 5)
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#define INTEL_PIPE_6BPC (2 << 5)
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#define INTEL_PIPE_12BPC (3 << 5)
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#define INTEL_PIPE_COLOR_SHIFT 5
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#define INTEL_PIPE_BPC(x) ((x) << INTEL_PIPE_COLOR_SHIFT)
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#define INTEL_PIPE_BPC_MASK (7 << INTEL_PIPE_COLOR_SHIFT)
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#define INTEL_PIPE_8BPC 0
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#define INTEL_PIPE_10BPC 1
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#define INTEL_PIPE_6BPC 2
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#define INTEL_PIPE_12BPC 3
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#define INTEL_PIPE_PROGRESSIVE (0 << 21)
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// cursors
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@ -917,6 +920,10 @@ struct intel_free_graphics_memory {
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#define FDI_RX_ENABLE (1 << 31)
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#define FDI_RX_PLL_ENABLED (1 << 13)
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#define FDI_RX_LINK_COLOR_SHIFT 16
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#define FDI_RX_LINK_BPC(x) ((x) << FDI_RX_LINK_COLOR_SHIFT)
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#define FDI_RX_LINK_BPC_MASK (7 << FDI_RX_LINK_COLOR_SHIFT)
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// Transcoder - same base as FDI_RX
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#define PCH_TRANS_CONF_A 0x0008
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#define PCH_TRANS_CONF_B 0x1008
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@ -103,6 +103,13 @@ FDITransmitter::EnablePLL(uint32 lanes)
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return;
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}
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value &= ~FDI_DP_PORT_WIDTH_MASK;
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value |= FDI_DP_PORT_WIDTH(lanes);
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//first update config, -then- enable PLL to be sure config is indeed updated
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write32(targetRegister, value);
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read32(targetRegister);
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write32(targetRegister, value | FDI_TX_PLL_ENABLED);
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read32(targetRegister);
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spin(100); // warmup 10us + dmi delay 20us, be generous
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@ -189,9 +196,17 @@ FDIReceiver::EnablePLL(uint32 lanes)
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return;
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}
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value &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
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//Link bit depth: this should be globally known per FDI link (i.e. laptop panel 3x6, rest 3x8)
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//currently using BIOS preconfigured setup
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//value &= ~FDI_DP_PORT_WIDTH_MASK;
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//value |= FDI_RX_LINK_BPC(INTEL_PIPE_8BPC);
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value &= ~FDI_DP_PORT_WIDTH_MASK;
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value |= FDI_DP_PORT_WIDTH(lanes);
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//value |= (read32(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
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//first update config, -then- enable PLL to be sure config is indeed updated
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write32(targetRegister, value);
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read32(targetRegister);
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write32(targetRegister, value | FDI_RX_PLL_ENABLED);
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read32(targetRegister);
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@ -239,38 +254,132 @@ FDILink::Train(display_mode* target)
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{
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CALLED();
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uint32 bitsPerPixel;
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switch (target->space) {
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case B_RGB32_LITTLE:
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bitsPerPixel = 32;
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status_t result = B_OK;
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uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
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uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
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//Link bit depth: this should be globally known per FDI link (i.e. laptop panel 3x6, rest 3x8)
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uint32 bitsPerPixel = ((read32(rxControl) & FDI_RX_LINK_BPC_MASK) >> FDI_RX_LINK_COLOR_SHIFT);
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switch (bitsPerPixel) {
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case INTEL_PIPE_8BPC:
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bitsPerPixel = 24;
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break;
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case B_RGB16_LITTLE:
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bitsPerPixel = 16;
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case INTEL_PIPE_10BPC:
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bitsPerPixel = 30;
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break;
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case B_RGB15_LITTLE:
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bitsPerPixel = 15;
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case INTEL_PIPE_6BPC:
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bitsPerPixel = 18;
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break;
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case INTEL_PIPE_12BPC:
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bitsPerPixel = 36;
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break;
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case B_CMAP8:
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default:
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bitsPerPixel = 8;
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break;
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ERROR("%s: FDI illegal link colordepth set.\n", __func__);
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return B_ERROR;
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}
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TRACE("%s: FDI Link Colordepth: %" B_PRIu32 "\n", __func__, bitsPerPixel);
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// Khz / 10. ( each output octet encoded as 10 bits.
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uint32 linkBandwidth = gInfo->shared_info->fdi_link_frequency * 1000 / 10;
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//Reserving 5% bandwidth for possible spread spectrum clock use
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uint32 bps = target->timing.pixel_clock * bitsPerPixel * 21 / 20;
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uint32 lanes = bps / (linkBandwidth * 8);
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//use DIV_ROUND_UP:
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uint32 lanes = (bps + (linkBandwidth * 8) - 1) / (linkBandwidth * 8);
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//remove below line when link training is to be done
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lanes = ((read32(txControl) & FDI_DP_PORT_WIDTH_MASK) >> FDI_DP_PORT_WIDTH_SHIFT) + 1;
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TRACE("%s: FDI Link Lanes: %" B_PRIu32 "\n", __func__, lanes);
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//assuming we'll only use link A and B (not C)
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if (lanes > 4) {
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result = B_ERROR;
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}
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if (result != B_OK) {
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ERROR("%s: FDI not enough lanes in hardware.\n", __func__);
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return result;
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}
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TRACE("%s: FDI TX ctrl: 0x%" B_PRIx32 "\n", __func__, read32(txControl));
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TRACE("%s: FDI RX ctrl: 0x%" B_PRIx32 "\n", __func__, read32(rxControl));
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#if 0
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//when link training is to be done re-enable this code
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//The order of handling things is important here..
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write32(txControl, read32(txControl) & ~FDI_TX_ENABLE);
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read32(txControl);
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write32(rxControl, read32(rxControl) & ~FDI_RX_ENABLE);
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read32(rxControl);
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write32(txControl, (read32(txControl) & ~FDI_LINK_TRAIN_NONE) | FDI_LINK_TRAIN_PATTERN_1);
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read32(txControl);
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if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
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write32(rxControl, (read32(rxControl) & ~FDI_LINK_TRAIN_PATTERN_MASK_CPT) | FDI_LINK_TRAIN_PATTERN_1_CPT);
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} else {
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write32(rxControl, (read32(rxControl) & ~FDI_LINK_TRAIN_NONE) | FDI_LINK_TRAIN_PATTERN_1);
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}
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read32(rxControl);
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spin(100);
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// Disable FDI clocks
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Receiver().SwitchClock(false);
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Transmitter().DisablePLL();
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Receiver().DisablePLL();
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#endif
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//Setup Data M/N
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uint64 linkspeed = lanes * linkBandwidth * 8;
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uint64 ret_n = 1;
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while(ret_n < linkspeed) {
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ret_n *= 2;
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}
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if (ret_n > 0x800000) {
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ret_n = 0x800000;
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}
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uint64 ret_m = target->timing.pixel_clock * ret_n * bitsPerPixel / linkspeed;
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while ((ret_n > 0xffffff) || (ret_m > 0xffffff)) {
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ret_m >>= 1;
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ret_n >>= 1;
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}
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//Set TU size bits (to default, max) before link training so that error detection works
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write32(Transmitter().Base() + PCH_FDI_PIPE_A_DATA_M1, ret_m | FDI_PIPE_MN_TU_SIZE_MASK);
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write32(Transmitter().Base() + PCH_FDI_PIPE_A_DATA_N1, ret_n);
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//Setup Link M/N
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linkspeed = linkBandwidth;
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ret_n = 1;
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while(ret_n < linkspeed) {
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ret_n *= 2;
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}
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if (ret_n > 0x800000) {
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ret_n = 0x800000;
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}
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ret_m = target->timing.pixel_clock * ret_n / linkspeed;
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while ((ret_n > 0xffffff) || (ret_m > 0xffffff)) {
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ret_m >>= 1;
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ret_n >>= 1;
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}
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write32(Transmitter().Base() + PCH_FDI_PIPE_A_LINK_M1, ret_m);
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//Writing Link N triggers all four registers to be activated also (on next VBlank)
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write32(Transmitter().Base() + PCH_FDI_PIPE_A_LINK_N1, ret_n);
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TRACE("%s: FDI data M1: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_DATA_M1));
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TRACE("%s: FDI data N1: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_DATA_N1));
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TRACE("%s: FDI link M1: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_LINK_M1));
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TRACE("%s: FDI link N1: 0x%" B_PRIx32 "\n", __func__, read32(Transmitter().Base() + PCH_FDI_PIPE_A_LINK_N1));
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//Set receiving end TU size bits to match sending end's setting
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write32(Receiver().Base() + PCH_FDI_RX_TRANS_UNIT_SIZE_1, FDI_RX_TRANS_UNIT_MASK);
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write32(Receiver().Base() + PCH_FDI_RX_TRANS_UNIT_SIZE_2, FDI_RX_TRANS_UNIT_MASK);
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#if 0
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//when link training is to be done re-enable this code
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// Enable FDI clocks
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Receiver().EnablePLL(lanes);
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Receiver().SwitchClock(true);
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Transmitter().EnablePLL(lanes);
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status_t result = B_ERROR;
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// TODO: Only _AutoTrain on IVYB Stepping B or later
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// otherwise, _ManualTrain
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if (gInfo->shared_info->device_type.Generation() >= 7)
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@ -281,6 +390,7 @@ FDILink::Train(display_mode* target)
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result = _IlkTrain(lanes);
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else
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result = _NormalTrain(lanes);
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#endif
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if (result != B_OK) {
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ERROR("%s: FDI training fault.\n", __func__);
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@ -580,6 +690,7 @@ FDILink::_AutoTrain(uint32 lanes)
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uint32 buffer = read32(txControl);
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// Clear port width selection and set number of lanes
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// fixme: does not belong in the train routines (?), (now) sits in FDI EnablePLL() routines
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buffer &= ~(7 << 19);
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buffer |= (lanes - 1) << 19;
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@ -589,6 +700,9 @@ FDILink::_AutoTrain(uint32 lanes)
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buffer &= ~FDI_LINK_TRAIN_NONE;
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write32(txControl, buffer);
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write32(Receiver().Base() + PCH_FDI_RX_MISC,
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FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
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bool trained = false;
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for (uint32 i = 0; i < (sizeof(gSnbBFDITrainParam)
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@ -599,10 +713,11 @@ FDILink::_AutoTrain(uint32 lanes)
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buffer &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
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buffer |= gSnbBFDITrainParam[i];
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write32(txControl, buffer | FDI_TX_ENABLE);
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read32(txControl);
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write32(rxControl, read32(rxControl) | FDI_RX_ENABLE);
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read32(rxControl);
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spin(5);
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spin(50);//looks like datasheet specified 5uS is not enough..?
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buffer = read32(txControl);
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if ((buffer & FDI_AUTO_TRAIN_DONE) != 0) {
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@ -612,6 +727,7 @@ FDILink::_AutoTrain(uint32 lanes)
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}
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write32(txControl, read32(txControl) & ~FDI_TX_ENABLE);
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read32(txControl);
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write32(rxControl, read32(rxControl) & ~FDI_RX_ENABLE);
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read32(rxControl);
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@ -628,11 +744,14 @@ FDILink::_AutoTrain(uint32 lanes)
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return B_ERROR;
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}
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// Enable ecc on IVB
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// Enable ecc on IVB (and disable test pattern at sending and receiving end)
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if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IVB)) {
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write32(rxControl, read32(rxControl)
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| FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
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read32(rxControl);
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//enable normal pixels (kill testpattern)
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write32(txControl, read32(txControl) | (0x3 << 8));
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read32(txControl);
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}
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return B_OK;
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@ -107,8 +107,10 @@ Pipe::Configure(display_mode* mode)
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//if (gInfo->shared_info->device_type.Generation() >= 4) {
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// pipeControl |= (INTEL_PIPE_DITHER_EN | INTEL_PIPE_DITHER_TYPE_SP);
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//Link bit depth, which is currently hardcoded to 8-bits per color
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pipeControl = (pipeControl & ~(0x7 << 5)) | INTEL_PIPE_8BPC;
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//Link bit depth: this should be globally known per FDI link (i.e. laptop panel 3x6, rest 3x8)
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//currently using BIOS preconfigured setup
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//pipeControl = (pipeControl & ~INTEL_PIPE_BPC_MASK) | INTEL_PIPE_BPC(INTEL_PIPE_8BPC);
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// TODO: CxSR downclocking?
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// TODO: Interlaced modes
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@ -356,7 +358,7 @@ Pipe::ConfigureClocks(const pll_divisors& divisors, uint32 pixelClock,
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// register which routes the PLL output to the transcoder that we need
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// to configure
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uint32 pllSel = read32(SNB_DPLL_SEL);
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TRACE("Old PLL selection: %x\n", pllSel);
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TRACE("Old PLL selection: 0x%" B_PRIx32 "\n", pllSel);
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uint32 shift = 0;
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uint32 pllIndex = 0;
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@ -381,7 +383,7 @@ Pipe::ConfigureClocks(const pll_divisors& divisors, uint32 pixelClock,
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// Set up the new configuration for this transcoder and enable it
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pllSel |= (8 | pllIndex) << shift;
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TRACE("New PLL selection: %x\n", pllSel);
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TRACE("New PLL selection: 0x%" B_PRIx32 "\n", pllSel);
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write32(SNB_DPLL_SEL, pllSel);
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}
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}
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@ -21,6 +21,7 @@
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#include "accelerant_protos.h"
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#include "FlexibleDisplayInterface.h"
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#include "intel_extreme.h"
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#include "PanelFitter.h"
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#include <new>
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@ -133,7 +134,7 @@ Port::SetPipe(Pipe* pipe)
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// FIXME is the use of PORT_TRANS_* constants correct for Sandy Bridge /
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// Cougar Point? Or is it only for Ivy Bridge / Panther point onwards?
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if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
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portState &= ~PORT_TRANS_SEL_MASK;
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portState &= ~PORT_TRANS_SEL_MASK; //fixme should be done sooner, not here!
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if (pipe->Index() == INTEL_PIPE_A)
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write32(portRegister, portState | PORT_TRANS_A_SEL_CPT);
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else
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@ -144,7 +145,6 @@ Port::SetPipe(Pipe* pipe)
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else
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write32(portRegister, portState | DISPLAY_MONITOR_PIPE_B);
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}
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fPipe = pipe;
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if (fPipe == NULL)
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@ -306,6 +306,7 @@ AnalogPort::_PortRegister()
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status_t
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AnalogPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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{
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CALLED();
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TRACE("%s: %s %dx%d\n", __func__, PortName(), target->virtual_width,
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target->virtual_height);
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@ -314,14 +315,13 @@ AnalogPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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return B_ERROR;
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}
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#if 0
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// Disabled for now as our code doesn't work. Let's hope VESA/EFI has
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// already set things up for us during boot.
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// Train FDI if it exists
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// Setup PanelFitter and Train FDI if it exists
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FDILink* link = fPipe->FDI();
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if (link != NULL)
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if (link != NULL) {
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// fixme insert fitter setup here
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link->Train(target);
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#endif
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}
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pll_divisors divisors;
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compute_pll_divisors(target, &divisors, false);
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@ -500,14 +500,13 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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}
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}
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#if 0
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// Disabled for now as our code doesn't work. Let's hope VESA/EFI has
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// already set things up for us during boot.
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// Train FDI if it exists
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// Setup PanelFitter and Train FDI if it exists
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FDILink* link = fPipe->FDI();
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if (link != NULL)
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if (link != NULL) {
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// fixme insert fitter setup here
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link->Train(target);
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#endif
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}
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// For LVDS panels, we may need to set the timings according to the panel
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// native video mode, and let the panel fitter do the scaling. But the
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@ -727,6 +726,7 @@ DigitalPort::_PortRegister()
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status_t
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DigitalPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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{
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CALLED();
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TRACE("%s: %s %dx%d\n", __func__, PortName(), target->virtual_width,
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target->virtual_height);
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@ -735,14 +735,13 @@ DigitalPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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return B_ERROR;
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}
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#if 0
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// Disabled for now as our code doesn't work. Let's hope VESA/EFI has
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// already set things up for us during boot.
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// Train FDI if it exists
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// Setup PanelFitter and Train FDI if it exists
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FDILink* link = fPipe->FDI();
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if (link != NULL)
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if (link != NULL) {
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// fixme insert fitter setup here
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link->Train(target);
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#endif
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}
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pll_divisors divisors;
|
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compute_pll_divisors(target, &divisors, false);
|
||||
@ -934,6 +933,7 @@ DisplayPort::_PortRegister()
|
||||
status_t
|
||||
DisplayPort::SetDisplayMode(display_mode* target, uint32 colorMode)
|
||||
{
|
||||
CALLED();
|
||||
TRACE("%s: %s %dx%d\n", __func__, PortName(), target->virtual_width,
|
||||
target->virtual_height);
|
||||
|
||||
@ -1095,6 +1095,7 @@ DigitalDisplayInterface::IsConnected()
|
||||
status_t
|
||||
DigitalDisplayInterface::SetDisplayMode(display_mode* target, uint32 colorMode)
|
||||
{
|
||||
CALLED();
|
||||
TRACE("%s: %s %dx%d\n", __func__, PortName(), target->virtual_width,
|
||||
target->virtual_height);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user