mirror of
https://review.haiku-os.org/haiku
synced 2025-02-01 11:15:59 +01:00
* add function to probe pll timing limits from AtomBIOS
* rename *_* pll vars to match style guidelines * refactor PLL calculation to be easier to read with more central 10kHz unit conversions * limited mode switching has been seen working including a perfect 1280x1024@75 git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42855 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
parent
c0fe7a011b
commit
cf1d1fb4ff
@ -552,6 +552,9 @@ detect_connectors()
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= encoderID;
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gConnector[connectorIndex]->encoder.type
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= encoderType;
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pll_limit_probe(
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&gConnector[connectorIndex]->encoder.pll);
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}
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}
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// END if object is encoder
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@ -28,20 +28,103 @@ extern "C" void _sPrintf(const char *format, ...);
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# define TRACE(x...) ;
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#endif
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#define ERROR(x...) _sPrintf("radeon_hd: " x)
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// For AtomBIOS PLLSet
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union set_pixel_clock {
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SET_PIXEL_CLOCK_PS_ALLOCATION base;
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PIXEL_CLOCK_PARAMETERS v1;
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PIXEL_CLOCK_PARAMETERS_V2 v2;
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PIXEL_CLOCK_PARAMETERS_V3 v3;
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PIXEL_CLOCK_PARAMETERS_V5 v5;
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PIXEL_CLOCK_PARAMETERS_V6 v6;
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union firmware_info {
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ATOM_FIRMWARE_INFO info;
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ATOM_FIRMWARE_INFO_V1_2 info_12;
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ATOM_FIRMWARE_INFO_V1_3 info_13;
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ATOM_FIRMWARE_INFO_V1_4 info_14;
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ATOM_FIRMWARE_INFO_V2_1 info_21;
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ATOM_FIRMWARE_INFO_V2_2 info_22;
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};
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static uint32
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pll_compute_post_divider(uint32 targetClock)
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status_t
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pll_limit_probe(pll_info *pll)
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{
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int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
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uint8 tableMajor;
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uint8 tableMinor;
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uint16 tableOffset;
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if (atom_parse_data_header(gAtomContext, index, NULL,
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&tableMajor, &tableMinor, &tableOffset) != B_OK) {
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ERROR("%s: Couldn't parse data header\n", __func__);
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return B_ERROR;
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}
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union firmware_info *firmwareInfo
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= (union firmware_info *)(gAtomContext->bios + tableOffset);
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/* pixel clock limits */
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pll->referenceFreq
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= B_LENDIAN_TO_HOST_INT16(firmwareInfo->info.usReferenceClock) * 10;
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if (tableMinor < 2) {
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pll->pllOutMin
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= B_LENDIAN_TO_HOST_INT16(
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firmwareInfo->info.usMinPixelClockPLL_Output) * 10;
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} else {
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pll->pllOutMin
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= B_LENDIAN_TO_HOST_INT32(
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firmwareInfo->info_12.ulMinPixelClockPLL_Output);
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}
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pll->pllOutMax
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= B_LENDIAN_TO_HOST_INT32(
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firmwareInfo->info.ulMaxPixelClockPLL_Output) * 10;
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if (tableMinor >= 4) {
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pll->lcdPllOutMin
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= B_LENDIAN_TO_HOST_INT16(
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firmwareInfo->info_14.usLcdMinPixelClockPLL_Output) * 100;
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if (pll->lcdPllOutMin == 0)
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pll->lcdPllOutMin = pll->pllOutMin;
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pll->lcdPllOutMax
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= B_LENDIAN_TO_HOST_INT16(
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firmwareInfo->info_14.usLcdMaxPixelClockPLL_Output) * 100;
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if (pll->lcdPllOutMax == 0)
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pll->lcdPllOutMax = pll->pllOutMax;
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} else {
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pll->lcdPllOutMin = pll->pllOutMin;
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pll->lcdPllOutMax = pll->pllOutMax;
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}
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if (pll->pllOutMin == 0) {
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pll->pllOutMin = 64800;
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// Avivo+ limit
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}
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pll->minPostDiv = POST_DIV_MIN;
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pll->maxPostDiv = POST_DIV_LIMIT;
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pll->minRefDiv = REF_DIV_MIN;
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pll->maxRefDiv = REF_DIV_LIMIT;
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pll->minFeedbackDiv = FB_DIV_MIN;
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pll->maxFeedbackDiv = FB_DIV_LIMIT;
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// pll->pllInMin = B_LENDIAN_TO_HOST_INT16(
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// firmware_info->info.usMinPixelClockPLL_Input) * 10;
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//
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// pll->pllInMax = B_LENDIAN_TO_HOST_INT16(
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// firmware_info->info.usMaxPixelClockPLL_Input) * 10;
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TRACE("%s: referenceFreq: %" B_PRIu16 "; pllOutMin: %" B_PRIu16 "; "
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" pllOutMax: %" B_PRIu16 "; pllInMin: %" B_PRIu16 ";"
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"pllInMax: %" B_PRIu16 "\n", __func__, pll->referenceFreq,
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pll->pllOutMin, pll->pllOutMax, pll->pllInMin, pll->pllInMax);
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return B_OK;
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}
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void
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pll_compute_post_divider(pll_info *pll)
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{
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radeon_shared_info &info = *gInfo->shared_info;
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@ -51,18 +134,20 @@ pll_compute_post_divider(uint32 targetClock)
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uint32 vco;
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if (info.device_chipset < (RADEON_R700 | 0x70)) {
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if (0) // TODO : RADEON_PLL_IS_LCD
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vco = PLL_MIN_DEFAULT / 10; // pll->lcd_pll_out_min;
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vco = pll->lcdPllOutMin;
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else
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vco = PLL_MIN_DEFAULT / 10; // pll->pll_out_min;
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vco = pll->pllOutMin;
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} else {
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if (0) // TODO : RADEON_PLL_IS_LCD
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vco = PLL_MAX_DEFAULT / 10; // pll->lcd_pll_out_max;
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vco = pll->lcdPllOutMax;
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else
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vco = PLL_MAX_DEFAULT / 10; // pll->pll_out_min;
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vco = pll->pllOutMin;
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}
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uint32 postDivider = vco / targetClock;
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uint32 tmp = vco % targetClock;
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TRACE("%s: vco = %" B_PRIu32 "\n", __func__, vco);
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uint32 postDivider = vco / pll->pixelClock;
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uint32 tmp = vco % pll->pixelClock;
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if (info.device_chipset < (RADEON_R700 | 0x70)) {
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if (tmp)
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@ -72,27 +157,28 @@ pll_compute_post_divider(uint32 targetClock)
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postDivider--;
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}
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if (postDivider > POST_DIV_LIMIT)
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postDivider = POST_DIV_LIMIT;
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else if (postDivider < POST_DIV_MIN)
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postDivider = POST_DIV_MIN;
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if (postDivider > pll->maxPostDiv)
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postDivider = pll->maxPostDiv;
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else if (postDivider < pll->minPostDiv)
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postDivider = pll->minPostDiv;
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return postDivider;
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pll->postDiv = postDivider;
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TRACE("%s: postDiv = %" B_PRIu32 "\n", __func__, postDivider);
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}
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status_t
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pll_compute(pll_info *pll) {
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pll_compute(pll_info *pll)
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{
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pll_compute_post_divider(pll);
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uint32 targetClock = pll->pixel_clock / 10;
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// to 10 kHz units
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uint32 targetClock = pll->pixelClock;
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pll->post_div = pll_compute_post_divider(targetClock);
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pll->reference_div = REF_DIV_MIN;
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pll->feedback_div = 0;
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pll->feedback_div_frac = 0;
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pll->feedbackDiv = 0;
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pll->feedbackDivFrac = 0;
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pll->referenceDiv = pll->minRefDiv;
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uint32 referenceFrequency = PLL_REFERENCE_DEFAULT / 10;
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uint32 referenceFrequency = pll->referenceFreq;
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// if RADEON_PLL_USE_REF_DIV
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// ref_div = pll->reference_div;
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@ -111,67 +197,68 @@ pll_compute(pll_info *pll) {
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// frac_fb_div = 0;
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// }
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// } else {
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while (pll->reference_div <= REF_DIV_LIMIT) {
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while (pll->referenceDiv <= pll->maxRefDiv) {
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// get feedback divider
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uint32 retroEncabulator = pll->post_div * pll->reference_div;
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uint32 retroEncabulator = pll->postDiv * pll->referenceDiv;
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retroEncabulator *= targetClock;
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pll->feedback_div = retroEncabulator / referenceFrequency;
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pll->feedback_div_frac
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pll->feedbackDiv = retroEncabulator / referenceFrequency;
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pll->feedbackDivFrac
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= retroEncabulator % referenceFrequency;
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if (pll->feedback_div > FB_DIV_LIMIT)
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pll->feedback_div = FB_DIV_LIMIT;
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else if (pll->feedback_div < FB_DIV_MIN)
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pll->feedback_div = FB_DIV_MIN;
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if (pll->feedbackDiv > pll->maxFeedbackDiv)
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pll->feedbackDiv = pll->maxFeedbackDiv;
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else if (pll->feedbackDiv < pll->minFeedbackDiv)
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pll->feedbackDiv = pll->minFeedbackDiv;
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if (pll->feedback_div_frac >= (referenceFrequency / 2))
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pll->feedback_div++;
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if (pll->feedbackDivFrac >= (referenceFrequency / 2))
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pll->feedbackDiv++;
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pll->feedback_div_frac = 0;
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if (pll->reference_div == 0
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|| pll->post_div == 0
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pll->feedbackDivFrac = 0;
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if (pll->referenceDiv == 0
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|| pll->postDiv == 0
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|| targetClock == 0) {
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TRACE("%s: Caught division by zero\n", __func__);
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TRACE("%s: Caught division by zero!\n", __func__);
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TRACE("%s: referenceDiv %" B_PRIu32 "\n", __func__, pll->referenceDiv);
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TRACE("%s: postDiv %" B_PRIu32 "\n", __func__, pll->postDiv);
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TRACE("%s: targetClock %" B_PRIu32 "\n", __func__, targetClock);
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return B_ERROR;
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}
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uint32 tmp = (referenceFrequency * pll->feedback_div)
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/ (pll->post_div * pll->reference_div);
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uint32 tmp = (referenceFrequency * pll->feedbackDiv)
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/ (pll->postDiv * pll->referenceDiv);
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tmp = (tmp * 10000) / targetClock;
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if (tmp > (10000 + MAX_TOLERANCE))
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pll->reference_div++;
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pll->referenceDiv++;
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else if (tmp >= (10000 - MAX_TOLERANCE))
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break;
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else
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pll->reference_div++;
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pll->referenceDiv++;
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}
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// }
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if (pll->reference_div == 0 || pll->post_div == 0) {
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if (pll->referenceDiv == 0 || pll->postDiv == 0) {
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TRACE("%s: Caught division by zero of post or reference divider\n",
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__func__);
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return B_ERROR;
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}
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uint32 calculatedClock
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= (referenceFrequency * pll->feedback_div)
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+ (referenceFrequency * pll->feedback_div_frac)
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/ (pll->reference_div * pll->post_div);
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calculatedClock *= 10;
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// back to kHz for storage
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= (referenceFrequency * pll->feedbackDiv)
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+ (referenceFrequency * pll->feedbackDivFrac)
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/ (pll->referenceDiv * pll->postDiv);
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TRACE("%s: pixel clock: %" B_PRIu32 " gives:"
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" feedbackDivider = %" B_PRIu32 ".%" B_PRIu32
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"; referenceDivider = %" B_PRIu32 "; postDivider = %" B_PRIu32 "\n",
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__func__, pll->pixel_clock, pll->feedback_div, pll->feedback_div_frac,
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pll->reference_div, pll->post_div);
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__func__, pll->pixelClock, pll->feedbackDiv, pll->feedbackDivFrac,
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pll->referenceDiv, pll->postDiv);
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if (pll->pixel_clock != calculatedClock) {
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if (pll->pixelClock != calculatedClock) {
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TRACE("%s: pixel clock %" B_PRIu32 " was changed to %" B_PRIu32 "\n",
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__func__, pll->pixel_clock, calculatedClock);
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pll->pixel_clock = calculatedClock;
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__func__, pll->pixelClock, calculatedClock);
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pll->pixelClock = calculatedClock;
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}
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return B_OK;
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@ -192,12 +279,12 @@ pll_adjust(pll_info *pll, uint8 crtcID)
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// TODO : PLL flags
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radeon_shared_info &info = *gInfo->shared_info;
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uint32 pixelClock = pll->pixel_clock;
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uint32 pixelClock = pll->pixelClock;
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// original as pixel_clock will be adjusted
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uint32 connectorIndex = gDisplay[crtcID]->connectorIndex;
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uint32 encoderID = gConnector[connectorIndex]->encoder.objectID;
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uint32 encoder_mode = display_get_encoder_mode(connectorIndex);
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uint32 encoderMode = display_get_encoder_mode(connectorIndex);
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if (info.device_chipset >= (RADEON_R600 | 0x20)) {
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union adjust_pixel_clock args;
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@ -221,7 +308,7 @@ pll_adjust(pll_info *pll, uint8 crtcID)
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args.v1.usPixelClock
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= B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
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args.v1.ucTransmitterID = encoderID;
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args.v1.ucEncodeMode = encoder_mode;
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args.v1.ucEncodeMode = encoderMode;
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// TODO : SS and SS % > 0
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if (0) {
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args.v1.ucConfig
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@ -230,15 +317,15 @@ pll_adjust(pll_info *pll, uint8 crtcID)
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atom_execute_table(gAtomContext, index, (uint32*)&args);
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// get returned adjusted clock
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pll->pixel_clock
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pll->pixelClock
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= B_LENDIAN_TO_HOST_INT16(args.v1.usPixelClock);
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pll->pixel_clock *= 10;
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pll->pixelClock *= 10;
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break;
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case 3:
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args.v3.sInput.usPixelClock
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= B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
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args.v3.sInput.ucTransmitterID = encoderID;
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args.v3.sInput.ucEncodeMode = encoder_mode;
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args.v3.sInput.ucEncodeMode = encoderMode;
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args.v3.sInput.ucDispPllConfig = 0;
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// TODO : SS and SS % > 0
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if (0) {
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@ -253,20 +340,21 @@ pll_adjust(pll_info *pll, uint8 crtcID)
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atom_execute_table(gAtomContext, index, (uint32*)&args);
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// get returned adjusted clock
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pll->pixel_clock
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pll->pixelClock
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= B_LENDIAN_TO_HOST_INT32(
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args.v3.sOutput.ulDispPllFreq);
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pll->pixel_clock *= 10;
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pll->pixelClock *= 10;
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// convert to kHz for storage
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if (args.v3.sOutput.ucRefDiv) {
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pll->flags |= PLL_USE_FRAC_FB_DIV;
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pll->flags |= PLL_USE_REF_DIV;
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pll->reference_div = args.v3.sOutput.ucRefDiv;
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pll->referenceDiv = args.v3.sOutput.ucRefDiv;
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}
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if (args.v3.sOutput.ucPostDiv) {
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pll->flags |= PLL_USE_FRAC_FB_DIV;
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pll->flags |= PLL_USE_POST_DIV;
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pll->post_div = args.v3.sOutput.ucPostDiv;
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pll->postDiv = args.v3.sOutput.ucPostDiv;
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}
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break;
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default:
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@ -283,19 +371,29 @@ pll_adjust(pll_info *pll, uint8 crtcID)
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}
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TRACE("%s: was: %" B_PRIu32 ", now: %" B_PRIu32 "\n", __func__,
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pixelClock, pll->pixel_clock);
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pixelClock, pll->pixelClock);
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return B_OK;
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}
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union set_pixel_clock {
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SET_PIXEL_CLOCK_PS_ALLOCATION base;
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PIXEL_CLOCK_PARAMETERS v1;
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PIXEL_CLOCK_PARAMETERS_V2 v2;
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PIXEL_CLOCK_PARAMETERS_V3 v3;
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PIXEL_CLOCK_PARAMETERS_V5 v5;
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PIXEL_CLOCK_PARAMETERS_V6 v6;
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};
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status_t
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pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
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{
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uint32 connectorIndex = gDisplay[crtcID]->connectorIndex;
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pll_info *pll = &gConnector[connectorIndex]->encoder.pll;
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pll->pixel_clock = pixelClock;
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pll->pixelClock = pixelClock;
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pll->id = pllID;
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pll_adjust(pll, crtcID);
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@ -319,33 +417,33 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
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switch (tableMinor) {
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case 1:
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args.v1.usPixelClock
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= B_HOST_TO_LENDIAN_INT16(pll->pixel_clock / 10);
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args.v1.usRefDiv = B_HOST_TO_LENDIAN_INT16(pll->reference_div);
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args.v1.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedback_div);
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args.v1.ucFracFbDiv = pll->feedback_div_frac;
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args.v1.ucPostDiv = pll->post_div;
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= B_HOST_TO_LENDIAN_INT16(pll->pixelClock / 10);
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args.v1.usRefDiv = B_HOST_TO_LENDIAN_INT16(pll->referenceDiv);
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args.v1.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedbackDiv);
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args.v1.ucFracFbDiv = pll->feedbackDivFrac;
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args.v1.ucPostDiv = pll->postDiv;
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args.v1.ucPpll = pll->id;
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args.v1.ucCRTC = crtcID;
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args.v1.ucRefDivSrc = 1;
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break;
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case 2:
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args.v2.usPixelClock
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= B_HOST_TO_LENDIAN_INT16(pll->pixel_clock / 10);
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args.v2.usRefDiv = B_HOST_TO_LENDIAN_INT16(pll->reference_div);
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args.v2.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedback_div);
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args.v2.ucFracFbDiv = pll->feedback_div_frac;
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args.v2.ucPostDiv = pll->post_div;
|
||||
= B_HOST_TO_LENDIAN_INT16(pll->pixelClock / 10);
|
||||
args.v2.usRefDiv = B_HOST_TO_LENDIAN_INT16(pll->referenceDiv);
|
||||
args.v2.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedbackDiv);
|
||||
args.v2.ucFracFbDiv = pll->feedbackDivFrac;
|
||||
args.v2.ucPostDiv = pll->postDiv;
|
||||
args.v2.ucPpll = pll->id;
|
||||
args.v2.ucCRTC = crtcID;
|
||||
args.v2.ucRefDivSrc = 1;
|
||||
break;
|
||||
case 3:
|
||||
args.v3.usPixelClock
|
||||
= B_HOST_TO_LENDIAN_INT16(pll->pixel_clock / 10);
|
||||
args.v3.usRefDiv = B_HOST_TO_LENDIAN_INT16(pll->reference_div);
|
||||
args.v3.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedback_div);
|
||||
args.v3.ucFracFbDiv = pll->feedback_div_frac;
|
||||
args.v3.ucPostDiv = pll->post_div;
|
||||
= B_HOST_TO_LENDIAN_INT16(pll->pixelClock / 10);
|
||||
args.v3.usRefDiv = B_HOST_TO_LENDIAN_INT16(pll->referenceDiv);
|
||||
args.v3.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedbackDiv);
|
||||
args.v3.ucFracFbDiv = pll->feedbackDivFrac;
|
||||
args.v3.ucPostDiv = pll->postDiv;
|
||||
args.v3.ucPpll = pll->id;
|
||||
args.v3.ucMiscInfo = (pll->id << 2);
|
||||
// if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
|
||||
@ -357,12 +455,12 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
|
||||
case 5:
|
||||
args.v5.ucCRTC = crtcID;
|
||||
args.v5.usPixelClock
|
||||
= B_HOST_TO_LENDIAN_INT16(pll->pixel_clock / 10);
|
||||
args.v5.ucRefDiv = pll->reference_div;
|
||||
args.v5.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedback_div);
|
||||
= B_HOST_TO_LENDIAN_INT16(pll->pixelClock / 10);
|
||||
args.v5.ucRefDiv = pll->referenceDiv;
|
||||
args.v5.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedbackDiv);
|
||||
args.v5.ulFbDivDecFrac
|
||||
= B_HOST_TO_LENDIAN_INT32(pll->feedback_div_frac * 100000);
|
||||
args.v5.ucPostDiv = pll->post_div;
|
||||
= B_HOST_TO_LENDIAN_INT32(pll->feedbackDivFrac * 100000);
|
||||
args.v5.ucPostDiv = pll->postDiv;
|
||||
args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
|
||||
// if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
|
||||
// args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
|
||||
@ -383,12 +481,12 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
|
||||
break;
|
||||
case 6:
|
||||
args.v6.ulDispEngClkFreq
|
||||
= B_HOST_TO_LENDIAN_INT32(crtcID << 24 | pll->pixel_clock / 10);
|
||||
args.v6.ucRefDiv = pll->reference_div;
|
||||
args.v6.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedback_div);
|
||||
= B_HOST_TO_LENDIAN_INT32(crtcID << 24 | pll->pixelClock / 10);
|
||||
args.v6.ucRefDiv = pll->referenceDiv;
|
||||
args.v6.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedbackDiv);
|
||||
args.v6.ulFbDivDecFrac
|
||||
= B_HOST_TO_LENDIAN_INT32(pll->feedback_div_frac * 100000);
|
||||
args.v6.ucPostDiv = pll->post_div;
|
||||
= B_HOST_TO_LENDIAN_INT32(pll->feedbackDivFrac * 100000);
|
||||
args.v6.ucPostDiv = pll->postDiv;
|
||||
args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
|
||||
// if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
|
||||
// args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
|
||||
@ -419,7 +517,7 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
|
||||
}
|
||||
|
||||
TRACE("%s: set adjusted pixel clock %" B_PRIu32 " (was %" B_PRIu32 ")\n",
|
||||
__func__, pll->pixel_clock, pixelClock);
|
||||
__func__, pll->pixelClock, pixelClock);
|
||||
|
||||
return atom_execute_table(gAtomContext, index, (uint32 *)&args);
|
||||
return atom_execute_table(gAtomContext, index, (uint32*)&args);
|
||||
}
|
||||
|
||||
@ -46,10 +46,7 @@
|
||||
|
||||
struct pll_info {
|
||||
/* pixel clock to be programmed (kHz)*/
|
||||
uint32 pixel_clock;
|
||||
|
||||
/* dot clock (kHz) */
|
||||
uint32 dot_clock;
|
||||
uint32 pixelClock;
|
||||
|
||||
/* flags for the current clock */
|
||||
uint32 flags;
|
||||
@ -58,35 +55,36 @@ struct pll_info {
|
||||
uint32 id;
|
||||
|
||||
/* reference frequency */
|
||||
uint32 reference_freq;
|
||||
uint32 referenceFreq;
|
||||
|
||||
/* fixed dividers */
|
||||
uint32 post_div;
|
||||
uint32 reference_div;
|
||||
uint32 feedback_div;
|
||||
uint32 feedback_div_frac;
|
||||
uint32 postDiv;
|
||||
uint32 referenceDiv;
|
||||
uint32 feedbackDiv;
|
||||
uint32 feedbackDivFrac;
|
||||
|
||||
/* pll in/out limits */
|
||||
uint32 pll_in_min;
|
||||
uint32 pll_in_max;
|
||||
uint32 pll_out_min;
|
||||
uint32 pll_out_max;
|
||||
uint32 lcd_pll_out_min;
|
||||
uint32 lcd_pll_out_max;
|
||||
uint32 best_vco;
|
||||
uint32 pllInMin;
|
||||
uint32 pllInMax;
|
||||
uint32 pllOutMin;
|
||||
uint32 pllOutMax;
|
||||
uint32 lcdPllOutMin;
|
||||
uint32 lcdPllOutMax;
|
||||
uint32 bestVco;
|
||||
|
||||
/* divider limits */
|
||||
uint32 min_ref_div;
|
||||
uint32 max_ref_div;
|
||||
uint32 min_post_div;
|
||||
uint32 max_post_div;
|
||||
uint32 min_feedback_div;
|
||||
uint32 max_feedback_div;
|
||||
uint32 min_frac_feedback_div;
|
||||
uint32 max_frac_feedback_div;
|
||||
uint32 minRefDiv;
|
||||
uint32 maxRefDiv;
|
||||
uint32 minPostDiv;
|
||||
uint32 maxPostDiv;
|
||||
uint32 minFeedbackDiv;
|
||||
uint32 maxFeedbackDiv;
|
||||
uint32 minFeedbackDivFrac;
|
||||
uint32 maxFeedbackDivFrac;
|
||||
};
|
||||
|
||||
|
||||
status_t pll_limit_probe(pll_info *pll);
|
||||
status_t pll_adjust(pll_info *pll, uint8 crtcID);
|
||||
status_t pll_compute(pll_info *pll);
|
||||
status_t pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user