This is no-op for 32 bit platforms because `int32` is defined as `long` there.
Change interrupt vector number from 64 bits to 32 bits for 64 bit platforms.
Change-Id: I52d1ad616cab16488804e9733c7afaf772a670ba
Reviewed-on: https://review.haiku-os.org/c/haiku/+/7507
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>
Also increase MSI message data size to 32 bits according to PCIe spec.
Remove 0xff check for MSI interrupts because it is potentially valid
interrupt vector number. Reject 0xff only for legacy pin interrupts.
- MSI-X supports up to 2048 interrupts per device that do not fit to
`uint8`.
- Non-x86 systems may use separate interrupt vector ranges for
hard-wired interrupts and MSI interrupts so `uint8` is not enough to
represent all of them.
Change-Id: Iaf9ffb197ec23db0f97ffe3ea756d28d7bfc8705
Reviewed-on: https://review.haiku-os.org/c/haiku/+/7433
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
after a0131eaae2884fdced27158c3d34732d1656aca9 mxcsr was possibly also incorrect.
fpu control and mxcsr will be restored with fxrstor/xrstor.
no need to clear pending exceptions on #MF
fix #18656 (and #18624 after reverting).
Change-Id: I7dd5e2e4610747c5b82abd6c67e302d264b4be92
Reviewed-on: https://review.haiku-os.org/c/haiku/+/7104
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
* also on x86 for simplicity.
* fixes #18624
* also makes x87 FPU data registers available for x87 floating instructions. EMMS is cheap.
see 25209d81f7
Change-Id: I5c1b399377102f3eb10bc6d7f7247afbaf6d8483
Reviewed-on: https://review.haiku-os.org/c/haiku/+/7089
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
Reviewed-by: Adrien Destugues <pulkomandy@pulkomandy.tk>
Only the x86 and PPC implementations look like they would have worked,
while the builtin is available and will work across all architectures.
We already use it unconditionally in some parts of libroot.
Change-Id: I2dffb3b2c7cdd605092382b9d649151adb921bb4
Reviewed-on: https://review.haiku-os.org/c/haiku/+/6942
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
ASID allocation is not supported yet, so always use ASID 0 for user pages for now.
Change-Id: I021e77dae692c22984bc625dd0588362bece45b7
Reviewed-on: https://review.haiku-os.org/c/haiku/+/6698
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Adrien Destugues <pulkomandy@pulkomandy.tk>
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>
* Introduce SWDBM flag similarly to the arm64 port
* Reuse TEX[2] for SWDBM flag which should be availble
to be used by the operating system if TEX remap
is enabled.
* Introduce SetAndClearPageTableEntryFlags for updating
accessed and modified flags atomically
* Startup sequence is handled similarly to accessed flag, i.e.
set Modified flag in initially mapped pages in bootloader and early map.
* Once the kernel initialization has progressed enough,
pages are mapped as read-only and modified flag handling is done
in the page fault handler.
Change-Id: I8f761e2c6325d1b91481abd569d5e8befded0761
Reviewed-on: https://review.haiku-os.org/c/haiku/+/6518
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Adrien Destugues <pulkomandy@pulkomandy.tk>
Before the PCI refactor, PCI initialization/enumeration occurred
immediately after the PCI module was loaded, and so by the time
we got to IOAPIC initialization, it was already complete.
After the refactor, PCI enumeration is deferred until slightly later,
and so we would try to initialize IO-APICs without knowing PCI
information. This would fail, as read_irq_routing_table needs to
have that available.
Hopefully fixes #18425, #18393, #18398.
Change-Id: I1e4b06367da26eeb10085a1c6322ed39885b632b
Reviewed-on: https://review.haiku-os.org/c/haiku/+/6476
Reviewed-by: X512 <danger_mail@list.ru>
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
Change-Id: Ia16e66a7bdac37019e6256405b9f10024909c69a
Reviewed-on: https://review.haiku-os.org/c/haiku/+/6215
Tested-by: Automation <automation@haiku-os.org>
Reviewed-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>
we detect basically the cpu info before loading the microcode,
to be able to detect the vendor, and avoid any update on hypervisor.
I couldn't test because my cpu doesn't have any update available.
Change-Id: I6aea830158423b3ee13b640be8a788fc9041e23c
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5859
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
tested on Zen2 (Ryzen 3 5300U)
This support was submitted in October for inclusion in Linux.
Haiku supports only two profiles. We could probably add some more, and let the driver says which it supports.
Change-Id: Id7754b445bc32a691d58a1e4af630351562abc22
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5826
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
* set PXN for all page tables below KERNEL_BASE
* also set PXN for physical page mapper
PXN, Privileged execute-never
When the PXN bit is 1, a Permission fault is generated if the processor
is executing at PL1 and attempts to execute an instruction fetched from
the corresponding memory region.
Change-Id: I3056cbed151004ac9edfbc81ebeada328aeb603c
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5607
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
Use the Privileged Only Thread ID Register aka TPIDRPRW to store
the current thread pointer.
The Privileged Only Thread ID Register is only accessible
in privileged modes, and is read/write.
see: ARMv7 Architecture Reference Manual,
section B3.12.46 CP15 c13 Software Thread ID registers
Change-Id: I5273bee8a80b78cdc547b2f6c96632d120eb3d55
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5608
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
GICv2 can use interrupt numbers up to 1019:
* 0-15 are SGIs aka ICIs
* 16-31 are PPIs
* 32-1019 are SPIs
Change-Id: I1c19be77105683da3f6988a5607b14dc10a899db
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5565
Reviewed-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Set AP[2:0] and XN flags based on page attributes.
PXN is not implemented as it seems to be available only
in L1 descriptors on ARMv7.
Set TEX, B, C flags based on memoryType:
* B_MTR_UC is mapped to Strongly Ordered (TEX=0, B=0, C=0)
* B_MTR_WC is mapped to Shareable Device Memory (TEX=0, B=1, C=0)
* B_MTR_WT is mapped to Outer and Inner Write-Through, no Write-Allocate (TEX=0, B=0, C=1)
* B_MTR_WB is mapped to Outer and Inner Write-Back, no Write-Allocate (TEx=0, B=1, C=1)
* B_MTR_WP has no direct equivalent on the ARM so it's mapped as B_MTR_WB
* default is Write-Back
Implement ARMPagingMethod32Bit::AttributesToPageTableEntryFlags()
for mapping from page attributes to AP[2:0] and XN flags.
Implement ARMPagingMethod32Bit::PageTableEntryFlagsToAttributes()
for the reverse mapping used in Query() and QueryInterrupt()
i.e. recover page attributes from AP[2:0] and XN flags.
Implement ARMPagingMethod32Bit::MemoryTypeToPageTableEntryFlags()
fr mapping from memoryType to TEX, B, C flags.
Implement ARMVMTranslationMap32Bit::Protect() which used to be commented out.
Accessed and modified flags are not implemented yet, so no such
flags are returned from Query() and QueryInterrupt().
Also because of this, we just invalidate TLB on any call to Protect()
without checking whether the page has been accessed.
Change-Id: I027af5c02bd6218d9f92a58044aeb26373e1956b
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5236
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
Reviewed-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Bootloader:
* set permissions to kernel read/write, no user access
for initially mapped memory areas
* set permissions to kernel read/write, no execute,
no user access for UART
Kernel:
* physical memory mapper uses kernel read/write mapping
with no-execute bit enabled
* all other pages are mapped as read/write/execute for
kernel and user
* proper access permissions and memory types to be
implemented later
Enforce memory access permissions by setting DACR to
client mode for domain #0, no access for other domains.
see ARM Architecture Reference Manual, section B3.7 Memory access control
and in particular the following subsections:
B3.7.1 Access permissions
B3.7.2 Execute-never restrictions on instruction fetching
B3.7.3 Domains, Short-descriptor format only
Change-Id: I8127b4c72dc516d013cb9751d80d6f3a9ec835e6
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5233
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
