Added AlderLake-P and AlderLake-N variants to agp_gart bus
and intel_extreme driver. Tested and confirmed working.
Change-Id: I1ac1e04fbba222a2f9eef483d68575665561e837
Reviewed-on: https://review.haiku-os.org/c/haiku/+/8840
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
The DPLL selection registers have changed again somewhere between
Skylake and Tiger Lake. Our code was trying to read/write the Skylake
registers on hardware where they don't exist anymore.
Introduce the new Tiger Lake registers and implement enough of it to get
things working on my machine (but probably only on my machine). Also
add a bit of specialization of DisplayPort which I think was not done
correctly on previous hardware either: for DisplayPort, the link rate is
selected from a handful of allowed frequencies, instead of closely
matching the pixel clock.
Things left TODO:
- Write a proper PLL allocation system to ensure each display gets
assigned its own PLL (unless multiple displays use the same timings).
For now it is hardcoded to what I want on my machine.
- Fix the DisplayPort PLL computation to use the values from Intel
datasheets, not the ones used by my machine which are somehow
different.
- Fix the DisplayPort PLL computation to select one of the several
available frequencies, allowing resolutions higher than Full HD which
require higher clocks.
- Fix DisplayPort link training or whatever must happen after the PLL is
set up, since changing the PLL results in a non-working display and we
don't get it back.
Unfortunately this still isn't enough to bring up both displays to life
at the same time. I think it is not very far, but the secondary display
(as decided by the BIOS) remains off for now even after successfully
setting it all up.
Early testing on other machines is welcome.
Change-Id: I37209bb14f32c99944bdc8ef6eef75e2550e18ed
Reviewed-on: https://review.haiku-os.org/c/haiku/+/7367
Reviewed-by: Alexander von Gluck <alex@terarocket.io>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Adrien Destugues <pulkomandy@pulkomandy.tk>
this needed for dp aux before skylake, only for DP A (eDP).
should help with #17771
Change-Id: I4bdcca1fdc05294fb5b56c5c96164b6936a5881e
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5355
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
* also uses the BAR size when dumping regs (as done by the intel_reg tool).
Change-Id: Ie29768afc8f9c42bb9a03b2866db34c4b0e43b7d
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5334
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
hraw_clock is possibly dynamic, but for the usecase this seems good enough.
Tested on SandyBridge and Haswell laptops.
Change-Id: I045b3c03f6b37bbffb3d8688658ffaa2a97311ae
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5319
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
* also handle dp aux on PCH.
* tested on Gen7, should work from Gen6.
Change-Id: I8d99bcdc10c817e66441a6a644df490dd988a74d
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5290
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
we enable every port interrupt instead of relying on the ports found in the VBT.
ATM only log the plug state when it changes.
Change-Id: I5175fb137d11f0114beb2915a4f363341cfe8e36
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5287
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
* BDB version from 111
* for DDI from Gen9
* for HDMI and DisplayPort from Gen6
* use the first port to create the mode list
* also probe DDI Port A
* the aux channel helps to select the correct dp aux registers.
Change-Id: I80549a6ec0477bed768cc5f388959b606d50c1b7
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5286
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
This assumes a Gen9 or Gen11 configuration, and aux channel 0. As a result, the same EDID will
be found for every DDI port. The mapping should be found in the VBT.
Tested on KabyLake and JasperLake
Change-Id: I27f5ac8ec8e6ba519fbe9aaf745e78a7361175b9
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5175
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
- Newer devices use a different layout for the backlight PWM registers
- Get the min brightness level from the BDB
Change-Id: I99745a022dd38733a4c2386f91c4c57016dd2acd
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5162
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Internal display on my laptop isn't detected yet so modesetting doesn't
work, but at least I get vblank interrupts and backlight control.
Fixes #17569
Change-Id: I86dd56bc3fc2c288688242e34d9220028036ab74
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5156
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
In most cases we don't need to use the complete display_mode struct and
we just need the timings. This will avoid future confusion between the
virtual width/height and the actual display timings, if we implement
scrolling someday.
Change-Id: I6c4430b84130b956a47ea0a01afb0843f5a34fd2
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4665
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
