474 Commits

Author SHA1 Message Date
Alexander von Gluck IV
d035469704 ARM: Name beagleboneblk back to beagle
* Pulkomandy pointed out that all Beagle hardware is
  very similar so we could likely get away with a single
  ARM target board.
2014-02-26 15:33:40 -06:00
Alexander von Gluck IV
8cfbbff4df ARM: Fix dmb opcode 2 on ARMv6
* Typo, also fix tabs
* Sorry for the spam, this should be correct now
2014-02-26 13:22:18 -06:00
Alexander von Gluck IV
b6994f96c0 ARM: Break apart ARMv5 and older dsb/dmb
* Add isb just because.
* pdziepak pointed out that ARMv5 and before
  had different barrier support.
* pdziepak also mentioned that dsb was too strong
  for __sync_synchronize
2014-02-26 13:17:21 -06:00
Alexander von Gluck IV
a21611e439 ARM: Add ARMv6 or older __sync_synchronize built-in
* On ARMv6 or older, we do a simulated dsb.
* Move __sync_synchronize into thread.c in libroot
  and use the new arch_atomic.h dsb/dmb defines.
* Gets arm @bootstrap-raw to end of bootstrap.
2014-02-26 12:51:51 -06:00
Alexander von Gluck IV
6d3363214f ARM: Simplify board specification
* Don't assume verdex as it isn't clear this was
  occurring.
* Make an educated guess on HAIKU_BOOT_PLATFORM
  based on provided board (but still allow it to
  be overridden)
* Error out if user doesn't populate
  HAIKU_BOOT_PLATFORM or enters an unknown board
  name.
* You need to add "-sHAIKU_BOOT_BOARD=xxx" to
  your jam to build for the proper ARM device.
* Rename beagle to beagleboneblk as per the
  documentation.
2014-02-26 00:27:18 -06:00
Ithamar R. Adema
5cef6be21f arm/atomic: fixup arch_atomic.h
* Remove _inline functions, since we're not using inlines
* Use compiler barrier instead of GCC builtin
2014-02-15 11:46:11 +01:00
Alexander von Gluck IV
35171b073d arm: Miscellaneous build fixes
* Use atomic_get_and_set for return value
* Atomics are no longer volatile
* Add missing arch_cpu_pause stub
* Move arch_cpu_idle to arch_cpu header to match
  other architectures
2014-02-12 23:37:15 -06:00
Alexander von Gluck IV
8018e8fa91 arm: Rework hrev46863 to use gcc built-in
* Those calls were indeed v7+ only, and our toolchain
  is v6.
2014-02-12 23:34:08 -06:00
Alexander von Gluck IV
92b2e03d0d arm: Add initial memory barrier functions
* These likely need reviewed by someone better
  at arm assembly. (#10537)
2014-02-12 23:11:11 -06:00
Pawel Dziepak
527da4ca8a x86[_64]: Separate bootloader and kernel GDT and IDT logic
From now on bootloader sets up its own minimal valid GDT and IDT. Then
the kernel replaces them with its own tables.
2014-01-28 00:44:02 +01:00
Pawel Dziepak
e1720098c6 kernel: No need for arch specific ifdefs in arch/atomic.h 2014-01-20 04:09:17 +01:00
Alexander von Gluck IV
c9e66bfc9b kernel: Add missing smp memory barrier calls. Set max cpu to 1
* Set max cpu to 1 for PPC until atomic functions are finished
* We have atomic functions inline in the kernel and assembly
  code in libroot post-scheduler merge... isn't that a lot of
  duplication?
2014-01-19 19:33:21 -06:00
Alexander von Gluck IV
fb8026e82b kernel: Add missing PPC CPU functions for idle / pause 2014-01-19 14:38:01 -06:00
Alexander von Gluck IV
524bea3553 kernel: fix missing cpu cache defines non-x86
* Regression introduced due to scheduler change
* Other other non-x86, non-ppc, and non-arm platforms
  need evalulated for this metric
2014-01-19 14:27:09 -06:00
Alexander von Gluck IV
6647d2c95a kernel: fix missing SMP_MAX_CPUS on non-x86
* Regression introduced due to scheduler change
* Drop MAX_BOOT_CPUS as it is no longer used
2014-01-19 14:09:51 -06:00
Pawel Dziepak
8cf8e53774 kernel/x86: Inline atomic functions and memory barriers 2014-01-06 09:08:53 +01:00
Pawel Dziepak
b89b5d3826 x86: Make arch/smp.h a C++ only header 2013-12-20 22:05:26 +01:00
Pawel Dziepak
6639514437 x86[_64]: Support assigning MSI IRQs to arbitrary CPU 2013-12-20 01:07:08 +01:00
Pawel Dziepak
e3d001ff02 x86: Implement multicast ICIs 2013-12-19 19:35:44 +01:00
Pawel Dziepak
735f67481f x86: Debugger can now use dr3 2013-12-17 04:31:29 +01:00
Pawel Dziepak
a5b070f1fa x86: Store pointer to the current thread in gs:0
Apparently, reading from dr3 is slower than reading from memory
with cache hit.

Also, depending on hypervisor configuration, accessing dr3 may cause
a VM exit (and, at least on kvm, it does), what makes it much slower
than a memory access even when there is a cache miss.
2013-12-17 04:08:51 +01:00
Pawel Dziepak
611376fef7 x86: Let each CPU have its own GDT 2013-12-17 03:57:20 +01:00
Pawel Dziepak
1bc7045fdf kernel, libroot: Introduce new API for obtaining system info 2013-12-16 03:58:43 +01:00
Pawel Dziepak
3e0e3be760 boot, kernel: Replace MAX_BOOT_CPUS with SMP_MAX_CPUS 2013-12-06 19:43:08 +01:00
Pawel Dziepak
7629d527c5 kernel: Use CPUSet in ICI code instead of cpu_mask_t 2013-12-06 03:08:39 +01:00
Pawel Dziepak
3514fd77f7 kernel: Reduce lock contention when processing ICIs 2013-11-29 03:36:44 +01:00
Pawel Dziepak
7db89e8dc3 kernel: Rework cpuidle module
* Create new interface for cpuidle modules (similar to the cpufreq
   interface)
 * Generic cpuidle module is no longer needed
 * Fix and update Intel C-State module
2013-11-25 23:50:27 +01:00
Pawel Dziepak
0e94a12f8e kernel: Make CACHE_LINE_ALIGN visible in the whole kernel 2013-11-25 00:35:15 +01:00
Pawel Dziepak
d897a478d7 kernel: Allow reassigning IRQs to logical processors 2013-11-18 04:55:25 +01:00
Pawel Dziepak
9c0ff0eed1 kernel: Add cpufreq module for Intel P-states
Since Sandy Bridge managing P-states on Intel processors is much easier
and more powerful than when using previous versions of EIST.
2013-10-30 00:55:03 +01:00
Pawel Dziepak
36cc64a9b3 x86[_64]: Add CPU cache topology detection for AMD and Intel CPUs 2013-10-02 23:48:03 +02:00
Pawel Dziepak
4110b730db x86[_64]: Add support for CPUID sub-leaves
Some CPUID leaves may contain one or more sub-leaves accessed by setting
ECX to an appropriate value.
2013-10-01 20:31:18 +02:00
Ithamar R. Adema
cc65466f0d ARM: kernel: Make KDL more useful on ARM
This adds the -mapcs-frame compiler flag for ARM to have "stable"
stack frames, adds support to the kernel for dumping stack crawls,
and initial support for iframes. There' much more functionality
to unlock in KDL, but this makes debugging already a lot more
comfortable.....
2013-09-17 23:04:59 +02:00
François Revol
c14bca2958 Merge branch 'master' into sam460ex 2013-09-14 01:16:51 +02:00
Jérôme Duval
0edcbd2754 apic: serialize writes to x2apic MSR...
as required by the specifications (it isn't needed with memory mapped i/o).
2013-08-26 21:48:33 +02:00
Jérôme Duval
787773400c Added x2APIC support.
* Mostly useful for virtualization at the moment. Works in QEmu.
* Can be enabled by safemode settings/menu.
* Please note that x2APIC normally requires use of VT-d interrupt remapping feature
on real hardware, which we don't support yet.
2013-08-26 21:08:21 +02:00
Jérôme Duval
46f7a54d8c MSI: Use the effective APIC id of the boot CPU for the address destination.
* This should only affect systems where the CPU ids aren't sequential (mostly
non Intel).
* Fixes #9807.
2013-07-29 17:36:03 +02:00
François Revol
eecde8e37c Merge branch 'master' into sam460ex 2013-04-21 01:34:20 +02:00
Pawel Dziepak
a8f8d2c057 x86_64: put user stack and team data at top of user address space 2013-04-04 20:54:56 +02:00
Pawel Dziepak
f697412ff8 vm: place commpage and team data near the top of user address space
Placing commpage and team user data somewhere at the top of the user accessible
virtual address space prevents these areas from conflicting with elf images
that require to be mapped at exact address (in most cases: runtime_loader).
2013-04-04 15:27:24 +02:00
Pawel Dziepak
966f207668 x86: enable data execution prevention
Set execute disable bit for any page that belongs to area with neither
B_EXECUTE_AREA nor B_KERNEL_EXECUTE_AREA set.

In order to take advanage of NX bit in 32 bit protected mode PAE must be
enabled. Thus, from now on it is also enabled when the CPU supports NX bit.

vm_page_fault() takes additional argument which indicates whether page fault
was caused by an illegal instruction fetch.
2013-04-04 15:22:23 +02:00
François Revol
d4eea7d43c Merge branch 'master' into sam460ex 2013-03-28 09:47:50 +01:00
Alex Smith
5e0c3db286 Account for the physical map area in the kernel VM space. Fixes #9547.
The physical memory map area was not included in the kernel virtual
address space range (it was below KERNEL_BASE). This caused problems
if an I/O operation took place on physical memory mapped there (the
bad address error seen in #9547 was occurring in lock_memory_etc()).
Changed KERNEL_BASE and KERNEL_SIZE to cover the area and add a null
area that covers all of it. Also changed X86VMTranslationMap64Bit to
handle large pages in Query(), as the physical map area uses large
pages.
2013-03-22 18:30:01 +00:00
François Revol
0acc7a44b6 PPC: Work-in-progress MMU definitions for AMCC440/460.
Unfinished. the TLB entries require setting 3 registers plus another
field for the PID.
Didn't yet decide how to store this in the page tables.
2013-03-09 03:26:53 +01:00
François Revol
97b9539c65 Merge branch 'master' into sam460ex 2012-12-06 00:12:40 +01:00
Michael Lotz
fd6e3a11e2 Use the existing ARM MMU definitions and remove duplicates. 2012-12-04 23:38:06 +01:00
Michael Lotz
50c463f4f1 Header cleanup, rename macros for more consistency. 2012-12-04 23:38:03 +01:00
François Revol
c435277d49 Merge branch 'master' into sam460ex 2012-11-29 16:06:28 +01:00
Michael Lotz
4818400fcf Add BCM2708 mailbox definitions and implementation.
The mailbox is used to communicate with the VideoCore on the rPi for
various tasks. First it will be used to configure the framebuffer.
2012-11-27 20:58:30 +01:00
André Hentschel
a8fe6dad7e Fix header protection for the beagle board 2012-11-26 17:59:53 +01:00