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The DPLL selection registers have changed again somewhere between Skylake and Tiger Lake. Our code was trying to read/write the Skylake registers on hardware where they don't exist anymore. Introduce the new Tiger Lake registers and implement enough of it to get things working on my machine (but probably only on my machine). Also add a bit of specialization of DisplayPort which I think was not done correctly on previous hardware either: for DisplayPort, the link rate is selected from a handful of allowed frequencies, instead of closely matching the pixel clock. Things left TODO: - Write a proper PLL allocation system to ensure each display gets assigned its own PLL (unless multiple displays use the same timings). For now it is hardcoded to what I want on my machine. - Fix the DisplayPort PLL computation to use the values from Intel datasheets, not the ones used by my machine which are somehow different. - Fix the DisplayPort PLL computation to select one of the several available frequencies, allowing resolutions higher than Full HD which require higher clocks. - Fix DisplayPort link training or whatever must happen after the PLL is set up, since changing the PLL results in a non-working display and we don't get it back. Unfortunately this still isn't enough to bring up both displays to life at the same time. I think it is not very far, but the secondary display (as decided by the BIOS) remains off for now even after successfully setting it all up. Early testing on other machines is welcome. Change-Id: I37209bb14f32c99944bdc8ef6eef75e2550e18ed Reviewed-on: https://review.haiku-os.org/c/haiku/+/7367 Reviewed-by: Alexander von Gluck <alex@terarocket.io> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org> Reviewed-by: Adrien Destugues <pulkomandy@pulkomandy.tk> |
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