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655f3b4161
other places where previously the same functionality was duplicated. Also seperated the header which was originally arch_smp.h into apic.h and arch_smp.h again as some of it is MP and not actually APIC. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@36182 a95241bf-73f2-0310-859d-f6bbb57e9c96
126 lines
3.8 KiB
C
126 lines
3.8 KiB
C
/*
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* Copyright 2008, Dustin Howett, dustin.howett@gmail.com. All rights reserved.
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* Copyright 2005, Axel Dörfler, axeld@pinc-software.de. All rights reserved.
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* Distributed under the terms of the MIT License.
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*
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* Copyright 2001-2002, Travis Geiselbrecht. All rights reserved.
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* Distributed under the terms of the NewOS License.
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*/
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#ifndef _KERNEL_ARCH_x86_APIC_H
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#define _KERNEL_ARCH_x86_APIC_H
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#include <boot/kernel_args.h>
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#include <SupportDefs.h>
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#define APIC_ENABLE 0x100
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#define APIC_FOCUS (~(1 << 9))
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#define APIC_SIV (0xff)
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// offsets to APIC register
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#define APIC_ID 0x020
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#define APIC_VERSION 0x030
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#define APIC_TASK_PRIORITY 0x080
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#define APIC_ARBITRATION_PRIORITY 0x090
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#define APIC_PROCESSOR_PRIORITY 0x0a0
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#define APIC_EOI 0x0b0
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#define APIC_LOGICAL_DEST 0x0d0
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#define APIC_DEST_FORMAT 0x0e0
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#define APIC_SPURIOUS_INTR_VECTOR 0x0f0
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#define APIC_ERROR_STATUS 0x280
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#define APIC_INTR_COMMAND_1 0x300 // bits 0-31
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#define APIC_INTR_COMMAND_2 0x310 // bits 32-63
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#define APIC_LVT_TIMER 0x320
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#define APIC_LVT_THERMAL_SENSOR 0x330
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#define APIC_LVT_PERFMON_COUNTERS 0x340
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#define APIC_LVT_LINT0 0x350
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#define APIC_LVT_LINT1 0x360
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#define APIC_LVT_ERROR 0x370
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#define APIC_INITIAL_TIMER_COUNT 0x380
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#define APIC_CURRENT_TIMER_COUNT 0x390
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#define APIC_TIMER_DIVIDE_CONFIG 0x3e0
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/* standard APIC interrupt defines */
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#define APIC_DELIVERY_MODE_FIXED 0
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#define APIC_DELIVERY_MODE_LOWESTPRI (1 << 8) // ICR1 only
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#define APIC_DELIVERY_MODE_SMI (2 << 8)
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#define APIC_DELIVERY_MODE_NMI (4 << 8)
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#define APIC_DELIVERY_MODE_INIT (5 << 8)
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#define APIC_DELIVERY_MODE_STARTUP (6 << 8) // ICR1 only
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#define APIC_DELIVERY_MODE_ExtINT (7 << 8) // LINT0/1 only
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#define APIC_DELIVERY_STATUS (1 << 12)
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#define APIC_TRIGGER_MODE_LEVEL (1 << 15)
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/* Interrupt Command defines */
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#define APIC_INTR_COMMAND_1_MASK 0xfff3f000
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#define APIC_INTR_COMMAND_2_MASK 0x00ffffff
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#define APIC_INTR_COMMAND_1_DEST_MODE_PHYSICAL 0
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#define APIC_INTR_COMMAND_1_DEST_MODE_LOGICAL (1 << 11)
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#define APIC_INTR_COMMAND_1_ASSERT (1 << 14)
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#define APIC_INTR_COMMAND_1_DEST_FIELD 0
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#define APIC_INTR_COMMAND_1_DEST_SELF (1 << 18)
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#define APIC_INTR_COMMAND_1_DEST_ALL (2 << 18)
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#define APIC_INTR_COMMAND_1_DEST_ALL_BUT_SELF (3 << 18)
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/* Local Vector Table defines */
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#define APIC_LVT_MASKED (1 << 16)
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// timer defines
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#define APIC_LVT_TIMER_MASK 0xfffcef00
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// LINT0/1 defines
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#define APIC_LVT_LINT_MASK 0xfffe0800
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#define APIC_LVT_LINT_INPUT_POLARITY (1 << 13)
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// Timer Divide Config Divisors
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#define APIC_TIMER_DIVIDE_CONFIG_1 0x0b
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#define APIC_TIMER_DIVIDE_CONFIG_2 0x00
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#define APIC_TIMER_DIVIDE_CONFIG_4 0x01
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#define APIC_TIMER_DIVIDE_CONFIG_8 0x02
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#define APIC_TIMER_DIVIDE_CONFIG_16 0x03
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#define APIC_TIMER_DIVIDE_CONFIG_32 0x08
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#define APIC_TIMER_DIVIDE_CONFIG_64 0x09
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#define APIC_TIMER_DIVIDE_CONFIG_128 0x0a
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/*
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#define APIC_LVT_DM 0x00000700
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#define APIC_LVT_DM_ExtINT 0x00000700
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#define APIC_LVT_DM_NMI 0x00000400
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#define APIC_LVT_IIPP 0x00002000
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#define APIC_LVT_TM 0x00008000
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#define APIC_LVT_M 0x00010000
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#define APIC_LVT_OS 0x00020000
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#define APIC_TPR_PRIO 0x000000ff
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#define APIC_TPR_INT 0x000000f0
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#define APIC_TPR_SUB 0x0000000f
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#define APIC_SVR_SWEN 0x00000100
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#define APIC_SVR_FOCUS 0x00000200
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#define IOAPIC_ID 0x0
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#define IOAPIC_VERSION 0x1
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#define IOAPIC_ARB 0x2
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#define IOAPIC_REDIR_TABLE 0x10
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#define IPI_CACHE_FLUSH 0x40
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#define IPI_INV_TLB 0x41
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#define IPI_INV_PTE 0x42
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#define IPI_INV_RESCHED 0x43
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#define IPI_STOP 0x44
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*/
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bool apic_available();
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uint32 apic_read(uint32 offset);
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void apic_write(uint32 offset, uint32 data);
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uint32 apic_local_id();
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void apic_end_of_interrupt();
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status_t apic_init(kernel_args *args);
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status_t apic_per_cpu_init(kernel_args *args, int32 cpu);
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#endif /* _KERNEL_ARCH_x86_APIC_H */
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