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107 lines
3.0 KiB
C
107 lines
3.0 KiB
C
/*
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* Copyright 2011-2012 Haiku, Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Alexander von Gluck, kallisti5@unixzen.com
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*/
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#ifndef __DEV_UART_PL011_H
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#define __DEV_UART_PL011_H
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#include <sys/types.h>
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#define PL01x_DR 0x00 // Data read or written
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#define PL01x_RSR 0x04 // Receive status, read
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#define PL01x_ECR 0x04 // Error clear, write
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#define PL010_LCRH 0x08 // Line control, high
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#define PL010_LCRM 0x0C // Line control, middle
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#define PL010_LCRL 0x10 // Line control, low
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#define PL010_CR 0x14 // Control
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#define PL01x_FR 0x18 // Flag (r/o)
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#define PL010_IIR 0x1C // Interrupt ID (r)
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#define PL010_ICR 0x1C // Interrupt clear (w)
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#define PL01x_ILPR 0x20 // IrDA low power
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#define PL011_IBRD 0x24 // Interrupt baud rate divisor
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#define PL011_FBRD 0x28 // Fractional baud rate divisor
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#define PL011_LCRH 0x2C // Line control
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#define PL011_CR 0x30 // Control
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#define PL011_IFLS 0x34 // Interrupt fifo level
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#define PL011_IMSC 0x38 // Interrupt mask
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#define PL011_RIS 0x3C // Raw interrupt
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#define PL011_MIS 0x40 // Masked interrupt
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#define PL011_ICR 0x44 // Interrupt clear
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#define PL011_DMACR 0x48 // DMA control register
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#define PL011_DR_OE (1 << 11)
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#define PL011_DR_BE (1 << 10)
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#define PL011_DR_PE (1 << 9)
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#define PL011_DR_FE (1 << 8)
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#define PL01x_RSR_OE 0x08
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#define PL01x_RSR_BE 0x04
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#define PL01x_RSR_PE 0x02
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#define PL01x_RSR_FE 0x01
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#define PL011_FR_RI 0x100
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#define PL011_FR_TXFE 0x080
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#define PL011_FR_RXFF 0x040
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#define PL01x_FR_TXFF 0x020
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#define PL01x_FR_RXFE 0x010
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#define PL01x_FR_BUSY 0x008
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#define PL01x_FR_DCD 0x004
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#define PL01x_FR_DSR 0x002
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#define PL01x_FR_CTS 0x001
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#define PL01x_FR_TMSK (PL01x_FR_TXFF | PL01x_FR_BUSY)
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#define PL011_CR_CTSEN 0x8000 // CTS flow control
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#define PL011_CR_RTSEN 0x4000 // RTS flow control
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#define PL011_CR_OUT2 0x2000 // OUT2
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#define PL011_CR_OUT1 0x1000 // OUT1
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#define PL011_CR_RTS 0x0800 // RTS
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#define PL011_CR_DTR 0x0400 // DTR
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#define PL011_CR_RXE 0x0200 // Receive enable
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#define PL011_CR_TXE 0x0100 // Transmit enable
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#define PL011_CR_LBR 0x0080 // Loopback enable
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#define PL011_CR_RTIE 0x0040
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#define PL011_CR_TIE 0x0020
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#define PL011_CR_RIE 0x0010
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#define PL011_CR_MSIE 0x0008
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#define PL011_CR_IIRLP 0x0004 // SIR low power mode
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#define PL011_CR_SIREN 0x0002 // SIR enable
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#define PL011_CR_UARTEN 0x0001 // UART enable
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#define PL011_LCRH_SPS 0x80
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#define PL01x_LCRH_WLEN_8 0x60
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#define PL01x_LCRH_WLEN_7 0x40
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#define PL01x_LCRH_WLEN_6 0x20
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#define PL01x_LCRH_WLEN_5 0x00
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#define PL01x_LCRH_FEN 0x10
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#define PL01x_LCRH_STP2 0x08
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#define PL01x_LCRH_EPS 0x04
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#define PL01x_LCRH_PEN 0x02
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#define PL01x_LCRH_BRK 0x01
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// TODO: Other PL01x registers + values?
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#ifdef __cplusplus
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extern "C" {
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#endif
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void uart_pl011_init_port(addr_t base, uint baud);
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void uart_pl011_init_early(void);
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void uart_pl011_init(addr_t base);
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int uart_pl011_putchar(addr_t base, char c);
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int uart_pl011_getchar(addr_t base, bool wait);
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void uart_pl011_flush_tx(addr_t base);
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void uart_pl011_flush_rx(addr_t base);
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#ifdef __cplusplus
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}
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#endif
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#endif
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