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83f755b5d8
Introduce memory barriers according to ARMARM, section G.5.3 TLB maintenance operations and barriers Sequence for mapping memory in (both L1 and L2): * DSB * Invalidate i-cache (TODO) * Insert new entry in page directory / page table * DSB * ISB Sequence for mapping memory out: * Remove page table entry * DSB * Invalidate TLB entry * DSB * ISB Sequence for updating a page table entry: * Update page table entry * DSB * Invalidate TLB entry * Invalidate branch predictor (TODO) * DSB * ISB Note: i-cache invalidation and branch predictor invalidation is not implemented yet as this commit focuses on implementing memory barriers. Change-Id: I192fa80f6b43117236a4be6fa8c988afca90e015 Reviewed-on: https://review.haiku-os.org/c/haiku/+/5241 Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org> Reviewed-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>
112 lines
1.9 KiB
C
112 lines
1.9 KiB
C
/*
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** Copyright 2003-2004, Axel Dörfler, axeld@pinc-software.de. All rights reserved.
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** Distributed under the terms of the MIT License.
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*/
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#ifndef _KERNEL_ARCH_ARM_CPU_H
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#define _KERNEL_ARCH_ARM_CPU_H
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#define CPU_MAX_CACHE_LEVEL 8
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#define CACHE_LINE_SIZE 64
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// TODO: Could be 32-bits sometimes?
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#define isb() __asm__ __volatile__("isb" : : : "memory")
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#define dsb() __asm__ __volatile__("dsb" : : : "memory")
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#define dmb() __asm__ __volatile__("dmb" : : : "memory")
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#define set_ac()
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#define clear_ac()
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#ifndef _ASSEMBLER
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#include <arch/arm/arch_thread_types.h>
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#include <kernel.h>
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/* raw exception frames */
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struct iframe {
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uint32 spsr;
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uint32 r0;
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uint32 r1;
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uint32 r2;
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uint32 r3;
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uint32 r4;
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uint32 r5;
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uint32 r6;
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uint32 r7;
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uint32 r8;
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uint32 r9;
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uint32 r10;
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uint32 r11;
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uint32 r12;
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uint32 usr_sp;
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uint32 usr_lr;
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uint32 svc_sp;
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uint32 svc_lr;
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uint32 pc;
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} _PACKED;
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/**! Values for arch_cpu_info.arch */
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enum {
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ARCH_ARM_PRE_ARM7,
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ARCH_ARM_v3,
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ARCH_ARM_v4,
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ARCH_ARM_v4T,
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ARCH_ARM_v5,
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ARCH_ARM_v5T,
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ARCH_ARM_v5TE,
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ARCH_ARM_v5TEJ,
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ARCH_ARM_v6,
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ARCH_ARM_v7
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};
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typedef struct arch_cpu_info {
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/* For a detailed interpretation of these values,
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see "The System Control coprocessor",
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"Main ID register" in your ARM ARM */
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int implementor;
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int part_number;
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int revision;
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int variant;
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int arch;
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} arch_cpu_info;
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern addr_t arm_get_far(void);
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extern int32 arm_get_fsr(void);
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extern addr_t arm_get_fp(void);
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extern int mmu_read_c1(void);
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extern int mmu_write_c1(int val);
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void arch_cpu_invalidate_TLB_page(addr_t page);
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static inline void
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arch_cpu_pause(void)
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{
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// TODO: ARM Priority pause call
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}
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static inline void
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arch_cpu_idle(void)
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{
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uint32 Rd = 0;
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asm volatile("mcr p15, 0, %[c7format], c7, c0, 4"
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: : [c7format] "r" (Rd) );
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}
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#ifdef __cplusplus
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};
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#endif
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#endif // !_ASSEMBLER
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#endif /* _KERNEL_ARCH_ARM_CPU_H */
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