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265899da3a
should help with #17664 register change from Tahiti for #17377 Change-Id: I52b9691cd6a04b58b70e905bc29e803f06936789 Reviewed-on: https://review.haiku-os.org/c/haiku/+/5526 Reviewed-by: John Scipione <jscipione@gmail.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
298 lines
6.5 KiB
C
298 lines
6.5 KiB
C
/*
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* Copyright 2006-2022, Haiku, Inc. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Axel Dörfler, axeld@pinc-software.de
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* Alexander von Gluck IV, kallisti5@unixzen.com
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*/
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#ifndef RADEON_HD_H
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#define RADEON_HD_H
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#include "lock.h"
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#include "radeon_reg.h"
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//#include "r500_reg.h" // Not used atm. DCE 0
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#include "avivo_reg.h" // DCE 1
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#include "r600_reg.h" // DCE 2
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#include "r700_reg.h" // DCE 3
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#include "evergreen_reg.h" // DCE 4
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#include "ni_reg.h" // DCE 5
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#include "si_reg.h" // DCE 6
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#include "sea_reg.h" // DCE 8
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#include "vol_reg.h" // DCE 10
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#include "car_reg.h" // DCE 11
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#include "pol_reg.h" // DCE 12
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#include <Accelerant.h>
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#include <Drivers.h>
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#include <edid.h>
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#include <PCI.h>
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#define VENDOR_ID_ATI 0x1002
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// Card chipset flags
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#define CHIP_STD (1 << 0) // Standard chipset
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#define CHIP_X2 (1 << 1) // Dual cpu
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#define CHIP_IGP (1 << 2) // IGP chipset
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#define CHIP_MOBILE (1 << 3) // Mobile chipset
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#define CHIP_DISCREET (1 << 4) // Discreet chipset
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#define CHIP_APU (1 << 5) // APU chipset
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#define DEVICE_NAME "radeon_hd"
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#define RADEON_ACCELERANT_NAME "radeon_hd.accelerant"
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#define MAX_NAME_LENGTH 32
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// Used to collect EDID from boot loader
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#define EDID_BOOT_INFO "vesa_edid/v1"
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#define MODES_BOOT_INFO "vesa_modes/v1"
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#define RHD_POWER_ON 0
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#define RHD_POWER_RESET 1 /* off temporarily */
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#define RHD_POWER_SHUTDOWN 2 /* long term shutdown */
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#define RHD_POWER_UNKNOWN 3 /* initial state */
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// Radeon Chipsets
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// !! Must match chipset names below
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enum radeon_chipset {
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RADEON_R420 = 0, //r400, Radeon X700-X850
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RADEON_R423,
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RADEON_RV410,
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RADEON_RS400,
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RADEON_RS480,
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RADEON_RS600,
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RADEON_RS690,
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RADEON_RS740,
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RADEON_RV515,
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RADEON_R520, //r500, DCE 1.0
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RADEON_RV530, // DCE 1.0
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RADEON_RV560, // DCE 1.0
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RADEON_RV570, // DCE 1.0
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RADEON_R580, // DCE 1.0
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RADEON_R600, //r600, DCE 2.0
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RADEON_RV610, // DCE 2.0
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RADEON_RV630, // DCE 2.0
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RADEON_RV670, // DCE 2.0
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RADEON_RV620, // DCE 3.0
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RADEON_RV635, // DCE 3.0
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RADEON_RS780, // DCE 3.0
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RADEON_RS880, // DCE 3.0
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RADEON_RV770, //r700, DCE 3.1
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RADEON_RV730, // DCE 3.2
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RADEON_RV710, // DCE 3.2
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RADEON_RV740, // DCE 3.2
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RADEON_CEDAR, //Evergreen, DCE 4.0
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RADEON_REDWOOD, // DCE 4.0
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RADEON_JUNIPER, // DCE 4.0
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RADEON_CYPRESS, // DCE 4.0
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RADEON_HEMLOCK, // DCE 4.0?
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RADEON_PALM, //Fusion APU (NI), DCE 4.1
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RADEON_SUMO, // DCE 4.1
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RADEON_SUMO2, // DCE 4.1
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RADEON_CAICOS, //Nothern Islands, DCE 5.0
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RADEON_TURKS, // DCE 5.0
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RADEON_BARTS, // DCE 5.0
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RADEON_CAYMAN, // DCE 5.0
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RADEON_ANTILLES, // DCE 5.0?
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RADEON_CAPEVERDE, //Southern Islands, DCE 6.0
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RADEON_PITCAIRN, // DCE 6.0
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RADEON_TAHITI, // DCE 6.0
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RADEON_ARUBA, // DCE 6.1 Trinity/Richland
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RADEON_OLAND, // DCE 6.4
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RADEON_HAINAN, // NO DCE, only compute
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RADEON_KAVERI, //Sea Islands, DCE 8.1
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RADEON_BONAIRE, // DCE 8.2
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RADEON_KABINI, // DCE 8.3
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RADEON_MULLINS, // DCE 8.3
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RADEON_HAWAII, // DCE 8.5
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RADEON_TOPAZ, //Volcanic Islands, NO DCE
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RADEON_TONGA, // DCE 10.0
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RADEON_FIJI, // DCE 10.1?
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RADEON_CARRIZO, // DCE 11.0
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RADEON_STONEY, // DCE 11.1?
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RADEON_POLARIS11, //Artic Islands, DCE 12.1?
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RADEON_POLARIS10, // DCE 12.0?
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RADEON_POLARIS12, // DCE 12.2?
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RADEON_VEGAM, // DCE 13.0?
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RADEON_VEGA10, // DCE 13.0?
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RADEON_VEGA12, // DCE 13.0?
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RADEON_VEGA20, // DCE 13.0?
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RADEON_RAVEN, // DCE 13?
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RADEON_NAVI, // DCE 13.0?
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};
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// !! Must match chipset families above
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static const char radeon_chip_name[][MAX_NAME_LENGTH] = {
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"R420",
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"R423",
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"RV410",
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"RS400",
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"RS480",
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"RS600",
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"RS690",
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"RS740",
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"RV515",
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"R520",
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"RV530",
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"RV560",
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"RV570",
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"R580",
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"R600",
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"RV610",
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"RV630",
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"RV670",
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"RV620",
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"RV635",
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"RS780",
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"RS880",
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"RV770",
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"RV730",
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"RV710",
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"RV740",
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"Cedar",
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"Redwood",
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"Juniper",
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"Cypress",
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"Hemlock",
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"Palm",
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"Sumo",
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"Sumo2",
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"Caicos",
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"Turks",
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"Barts",
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"Cayman",
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"Antilles",
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"Cape Verde",
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"Pitcairn",
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"Tahiti",
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"Aruba",
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"Oland",
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"Hainan",
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"Kaveri",
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"Bonaire",
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"Kabini",
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"Mullins",
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"Hawaii",
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"Topaz",
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"Tonga",
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"Fiji",
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"Carrizo",
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"Stoney Ridge",
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"Polaris 11",
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"Polaris 10",
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"Polaris 12",
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"Vega Mobile",
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"Vega 10",
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"Vega 12",
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"Vega 20",
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"Raven",
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"Navi",
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};
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struct ring_buffer {
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struct lock lock;
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uint32 register_base;
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uint32 offset;
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uint32 size;
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uint32 position;
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uint32 space_left;
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uint8* base;
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};
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struct radeon_shared_info {
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uint32 deviceIndex; // accelerant index
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uint32 pciID; // device pci id
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uint32 pciRev; // device pci revision
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area_id mode_list_area; // area containing display mode list
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uint32 mode_count;
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bool has_rom; // was rom mapped?
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area_id rom_area; // area of mapped rom
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uint32 rom_phys; // rom base location
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uint32 rom_size; // rom size
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uint8* rom; // cloned, memory mapped PCI ROM
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display_mode current_mode;
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uint32 bytes_per_row;
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uint32 bits_per_pixel;
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uint32 dpms_mode;
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area_id registers_area; // area of memory mapped registers
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uint8* status_page;
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addr_t physical_status_page;
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uint32 graphics_memory_size;
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uint8* frame_buffer; // virtual memory mapped FB
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area_id frame_buffer_area; // area of memory mapped FB
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addr_t frame_buffer_phys; // card PCI BAR address of FB
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uint32 frame_buffer_size; // FB size mapped
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bool has_edid;
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edid1_info edid_info;
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struct lock accelerant_lock;
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struct lock engine_lock;
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ring_buffer primary_ring_buffer;
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char deviceName[MAX_NAME_LENGTH];
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uint16 chipsetID;
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char chipsetName[MAX_NAME_LENGTH];
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uint32 chipsetFlags;
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uint8 dceMajor;
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uint8 dceMinor;
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uint16 color_data[3 * 256]; // colour lookup table
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};
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//----------------- ioctl() interface ----------------
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// magic code for ioctls
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#define RADEON_PRIVATE_DATA_MAGIC 'rdhd'
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// list ioctls
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enum {
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RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
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RADEON_GET_DEVICE_NAME,
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RADEON_ALLOCATE_GRAPHICS_MEMORY,
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RADEON_FREE_GRAPHICS_MEMORY
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};
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// retrieve the area_id of the kernel/accelerant shared info
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struct radeon_get_private_data {
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uint32 magic; // magic number
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area_id shared_info_area;
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};
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// allocate graphics memory
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struct radeon_allocate_graphics_memory {
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uint32 magic;
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uint32 size;
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uint32 alignment;
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uint32 flags;
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uint32 buffer_base;
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};
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// free graphics memory
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struct radeon_free_graphics_memory {
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uint32 magic;
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uint32 buffer_base;
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};
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// registers
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#define R6XX_CONFIG_APER_SIZE 0x5430 // r600>
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#define OLD_CONFIG_APER_SIZE 0x0108 // <r600
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#define CONFIG_MEMSIZE 0x5428 // r600>
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#define CONFIG_MEMSIZE_TAHITI 0x03de // tahiti>
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#endif /* RADEON_HD_H */
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