X512 fa557843f2 riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.

Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883
Reviewed-by: X512 <danger_mail@list.ru>
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
2022-12-11 18:43:15 +00:00

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C

/*
* Copyright 2003-2004, Axel Dörfler, axeld@pinc-software.de.
* Copyright 2019, Adrien Destugues, pulkomandy@pulkomandy.tk.
* Distributed under the terms of the MIT License.
*/
#ifndef _KERNEL_ARCH_RISCV64_CPU_H
#define _KERNEL_ARCH_RISCV64_CPU_H
#include <arch/riscv64/arch_thread_types.h>
#include <arch_cpu_defs.h>
#include <kernel.h>
#define CPU_MAX_CACHE_LEVEL 8
#define CACHE_LINE_SIZE 64
static inline bool
get_ac()
{
return SstatusReg{.val = Sstatus()}.sum;
}
static inline void
set_ac()
{
SetBitsSstatus(SstatusReg{.sum = 1}.val);
}
static inline void
clear_ac()
{
ClearBitsSstatus(SstatusReg{.sum = 1}.val);
}
typedef struct arch_cpu_info {
uint64 hartId;
} arch_cpu_info;
#ifdef __cplusplus
extern "C" {
#endif
void __riscv64_setup_system_time(uint64 conversionFactor);
static inline void
arch_cpu_pause(void)
{
// TODO: CPU pause
}
static inline void
arch_cpu_idle(void)
{
Wfi();
}
#ifdef __cplusplus
}
#endif
#endif /* _KERNEL_ARCH_RISCV64_CPU_H */