X512 fa557843f2 riscv: use atomic CSR bit set/clear operations, refactor
Fix race conditions that cause broken timer interrupts.

Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883
Reviewed-by: X512 <danger_mail@list.ru>
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
2022-12-11 18:43:15 +00:00
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