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Copying binutils 2.16.1 into trunk.

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git-svn-id: file:///srv/svn/repos/haiku/buildtools/trunk@15075 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Ingo Weinhold
2005-11-22 16:32:10 +00:00
parent b67b6a17a6
commit 6809759e16
6524 changed files with 2437246 additions and 0 deletions
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2005-02-24 Alan Modra <amodra@bigpond.net.au>
* frv.opc (parse_A): Warning fix.
2005-02-23 Nick Clifton <nickc@redhat.com>
* frv.opc: Fixed compile time warnings about differing signed'ness
of pointers passed to functions.
* m32r.opc: Likewise.
2005-02-11 Nick Clifton <nickc@redhat.com>
* iq2000.opc (parse_jtargq10): Change type of valuep argument to
'bfd_vma *' in order avoid compile time warning message.
2005-01-28 Hans-Peter Nilsson <hp@axis.com>
* cris.cpu (mstep): Add missing insn.
2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
* frv.cpu: Add support for TLS annotations in loads and calll.
* frv.opc (parse_symbolic_address): New.
(parse_ldd_annotation): New.
(parse_call_annotation): New.
(parse_ld_annotation): New.
(parse_ulo16, parse_uslo16): Use parse_symbolic_address.
Introduce TLS relocations.
(parse_d12, parse_s12, parse_u12): Likewise.
(parse_uhi16): Likewise. Fix constant checking on 64-bit host.
(parse_call_label, print_at): New.
2004-12-21 Mikael Starvik <starvik@axis.com>
* cris.cpu (cris-set-mem): Correct integral write semantics.
2004-11-29 Hans-Peter Nilsson <hp@axis.com>
* cris.cpu: New file.
2004-11-15 Michael K. Lechner <mike.lechner@gmail.com>
* iq2000.cpu: Added quotes around macro arguments so that they
will work with newer versions of guile.
2004-10-27 Nick Clifton <nickc@redhat.com>
* iq2000m.cpu (pkrlr1, pkrlr30, rbr1, rbr30, rxr1, rxr30, wbr1,
wbr1u, wbr30, wbr30u, wxr1, wxr1u, wxr30, wxr30u): Add an index
operand.
* iq2000.cpu (dnop index): Rename to _index to avoid complications
with guile.
2004-08-27 Richard Sandiford <rsandifo@redhat.com>
* frv.cpu (cfmovs): Change UNIT attribute to FMALL.
2004-05-15 Nick Clifton <nickc@redhat.com>
* iq2000.opc (iq2000_cgen_insn_supported): Make 'insn' argument const.
2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* m32r.opc (parse_hi16): Fixed shigh(0xffff8000) bug.
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* frv.cpu (define-arch frv): Add fr450 mach.
(define-mach fr450): New.
(define-model fr450): New. Add profile units to every fr450 insn.
(define-attr UNIT): Add MDCUTSSI.
(define-attr FR450-MAJOR): New enum. Add to every fr450 insn.
(define-attr AUDIO): New boolean.
(f-LRAE, f-LRAD, f-LRAS, f-TLBPRopx, f-TLBPRL)
(f-LRA-null, f-TLBPR-null): New fields.
(scr0, scr1, scr2, scr3, imavr1, damvr1, cxnr, ttbr)
(tplr, tppr, tpxr, timerh, timerl, timerd, btbr): New SPRs.
(LRAE, LRAD, LRAS, TLBPRopx, TLBPRL): New operands.
(LRA-null, TLBPR-null): New macros.
(iacc-multiply-r-r, slass, scutss, int-arith-ss-r-r): Add AUDIO attr.
(load-real-address): New macro.
(lrai, lrad, tlbpr): New instructions.
(media-cut-acc, media-cut-acc-ss): Add fr450-major argument.
(mcut, mcuti, mcutss, mcutssi): Adjust accordingly.
(mdcutssi): Change UNIT attribute to MDCUTSSI.
(media-low-clear-semantics, media-scope-limit-semantics)
(media-quad-limit, media-quad-shift): New macros.
(mqlclrhs, mqlmths, mqsllhi, mqsrahi): New instructions.
* frv.opc (frv_is_branch_major, frv_is_float_major, frv_is_media_major)
(frv_is_branch_insn, frv_is_float_insn, frv_is_media_insn)
(frv_vliw_reset, frv_vliw_add_insn): Handle bfd_mach_fr450.
(fr450_unit_mapping): New array.
(fr400_unit_mapping, fr500_unit_mapping, fr550_unit_mapping): Add entry
for new MDCUTSSI unit.
(fr450_check_insn_major_constraints): New function.
(check_insn_major_constraints): Use it.
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
(scutss): Change unit to I0.
(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
(mqsaths): Fix FR400-MAJOR categorization.
(media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
(media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
* frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
combinations.
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
(rstb, rsth, rst, rstd, rstq): Delete.
(rstbf, rsthf, rstf, rstdf, rstqf): Delete.
2004-02-23 Nick Clifton <nickc@redhat.com>
* Apply these patches from Renesas:
2004-02-10 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* cpu/m32r.opc (my_print_insn): Fixed incorrect output when
disassembling codes for 0x*2 addresses.
2003-12-15 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* cpu/m32r.cpu: Add PIPE_O attribute to "pop" instruction.
2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* cpu/m32r.cpu : Add new model m32r2.
Add new instructions.
Replace occurrances of 'Mitsubishi' with 'Renesas'.
Changed PIPE attr of push from O to OS.
Care for Little-endian of M32R.
* cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
Care for Little-endian of M32R.
(parse_slo16): signed extension for value.
2004-02-20 Andrew Cagney <cagney@redhat.com>
* m32r.opc, m32r.cpu: New files. Written by , Doug Evans, Nick
Clifton, Ben Elliston, Matthew Green, and Andrew Haley.
* sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all
written by Ben Elliston.
2004-01-14 Richard Sandiford <rsandifo@redhat.com>
* frv.cpu (UNIT): Add IACC.
(iacc-multiply-r-r): Use it.
* frv.opc (fr400_unit_mapping): Add entry for IACC.
(fr500_unit_mapping, fr550_unit_mapping): Likewise.
2004-01-06 Alexandre Oliva <aoliva@redhat.com>
2003-12-19 Alexandre Oliva <aoliva@redhat.com>
* frv.opc (parse_ulo16, parse_uhi16, parse_d12): Fix some
cut&paste errors in shifting/truncating numerical operands.
2003-08-08 Alexandre Oliva <aoliva@redhat.com>
* frv.opc (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
(parse_uslo16): Likewise.
(parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
(parse_d12): Parse gotoff12 and gotofffuncdesc12.
(parse_s12): Likewise.
2003-08-04 Alexandre Oliva <aoliva@redhat.com>
* frv.opc (parse_ulo16): Parse gotlo and gotfuncdesclo.
(parse_uslo16): Likewise.
(parse_uhi16): Parse gothi and gotfuncdeschi.
(parse_d12): Parse got12 and gotfuncdesc12.
(parse_s12): Likewise.
2003-10-10 Dave Brolley <brolley@redhat.com>
* frv.cpu (dnpmop): New p-macro.
(GRdoublek): Use dnpmop.
(CPRdoublek, FRdoublei, FRdoublej, FRdoublek): Ditto.
(store-double-r-r): Use (.sym regtype doublek).
(r-store-double): Ditto.
(store-double-r-r-u): Ditto.
(conditional-store-double): Ditto.
(conditional-store-double-u): Ditto.
(store-double-r-simm): Ditto.
(fmovs): Assign to UNIT FMALL.
2003-10-06 Dave Brolley <brolley@redhat.com>
* frv.cpu, frv.opc: Add support for fr550.
2003-09-24 Dave Brolley <brolley@redhat.com>
* frv.cpu (u-commit): New modelling unit for fr500.
(mwtaccg): Use frv_ref_SI to reference ACC40Sk as an input operand.
(commit-r): Use u-commit model for fr500.
(commit): Ditto.
(conditional-float-binary-op): Take profiling data as an argument.
Update callers.
(ne-float-binary-op): Ditto.
2003-09-19 Michael Snyder <msnyder@redhat.com>
* frv.cpu (nldqi): Delete unimplemented instruction.
2003-09-12 Dave Brolley <brolley@redhat.com>
* frv.cpu (u-clrgr, u-clrfr): New units of model fr500.
(clear-ne-flag-r): Pass insn profiling in as an argument. Call
frv_ref_SI to get input register referenced for profiling.
(clear-ne-flag-all): Pass insn profiling in as an argument.
(clrgr,clrfr,clrga,clrfa): Add profiling information.
2003-09-11 Michael Snyder <msnyder@redhat.com>
* frv.cpu: Typographical corrections.
2003-09-09 Dave Brolley <brolley@redhat.com>
* frv.cpu (media-dual-complex): Change UNIT to FMALL.
(conditional-media-dual-complex, media-quad-complex): Likewise.
2003-09-04 Dave Brolley <brolley@redhat.com>
* frv.cpu (register-transfer): Pass in all attributes in on argument.
Update all callers.
(conditional-register-transfer): Ditto.
(cache-preload): Ditto.
(floating-point-conversion): Ditto.
(floating-point-neg): Ditto.
(float-abs): Ditto.
(float-binary-op-s): Ditto.
(conditional-float-binary-op): Ditto.
(ne-float-binary-op): Ditto.
(float-dual-arith): Ditto.
(ne-float-dual-arith): Ditto.
2003-09-03 Dave Brolley <brolley@redhat.com>
* frv.opc (parse_A, parse_A0, parse_A1): New parse handlers.
* frv.cpu (UNIT): Add IALL, FMALL, FMLOW, STORE, SCAN, DCPL, MDUALACC,
MCLRACC-1.
(A): Removed operand.
(A0,A1): New operands replace operand A.
(mnop): Now a real insn
(mclracc): Removed insn.
(mclracc-0, mclracc-1): New insns replace mclracc.
(all insns): Use new UNIT attributes.
2003-08-21 Nick Clifton <nickc@redhat.com>
* frv.cpu (mbtoh): Replace input parameter to u-media-dual-expand
and u-media-dual-btoh with output parameter.
(cmbtoh): Add profiling hack.
2003-08-19 Michael Snyder <msnyder@redhat.com>
* frv.cpu: Fix typo, Frintkeven -> FRintkeven
2003-06-10 Doug Evans <dje@sebabeach.org>
* frv.cpu: Add IDOC attribute.
2003-06-06 Andrew Cagney <cagney@redhat.com>
Contributed by Red Hat.
* iq2000.cpu: New file. Written by Ben Elliston, Jeff Johnston,
Stan Cox, and Frank Ch. Eigler.
* iq2000.opc: New file. Written by Ben Elliston, Frank
Ch. Eigler, Chris Moller, Jeff Johnston, and Stan Cox.
* iq2000m.cpu: New file. Written by Jeff Johnston.
* iq10.cpu: New file. Written by Jeff Johnston.
2003-06-05 Nick Clifton <nickc@redhat.com>
* frv.cpu (FRintieven): New operand. An even-numbered only
version of the FRinti operand.
(FRintjeven): Likewise for FRintj.
(FRintkeven): Likewise for FRintk.
(mdcutssi, media-dual-word-rotate-r-r, mqsaths,
media-quad-arith-sat-semantics, media-quad-arith-sat,
conditional-media-quad-arith-sat, mdunpackh,
media-quad-multiply-semantics, media-quad-multiply,
conditional-media-quad-multiply, media-quad-complex-i,
media-quad-multiply-acc-semantics, media-quad-multiply-acc,
conditional-media-quad-multiply-acc, munpackh,
media-quad-multiply-cross-acc-semantics, mdpackh,
media-quad-multiply-cross-acc, mbtoh-semantics,
media-quad-cross-multiply-cross-acc-semantics,
media-quad-cross-multiply-cross-acc, mbtoh, mhtob-semantics,
media-quad-cross-multiply-acc-semantics, cmbtoh,
media-quad-cross-multiply-acc, media-quad-complex, mhtob,
media-expand-halfword-to-double-semantics, mexpdhd, cmexpdhd,
cmhtob): Use new operands.
* frv.opc (CGEN_VERBOSE_ASSEMBLER_ERRORS): Define.
(parse_even_register): New function.
2003-06-03 Nick Clifton <nickc@redhat.com>
* frv.cpu (media-dual-word-rotate-r-r): Use a signed 6-bit
immediate value not unsigned.
2003-06-03 Andrew Cagney <cagney@redhat.com>
Contributed by Red Hat.
* frv.cpu: New file. Written by Dave Brolley, Catherine Moore,
and Eric Christopher.
* frv.opc: New file. Written by Catherine Moore, and Dave
Brolley.
* simplify.inc: New file. Written by Doug Evans.
2003-05-02 Andrew Cagney <cagney@redhat.com>
* New file.
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:

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/* IQ2000 opcode support. -*- C -*-
Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
Contributed by Red Hat Inc; developed under contract from Fujitsu.
This file is part of the GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* This file is an addendum to iq2000.cpu. Heavy use of C code isn't
appropriate in .cpu files, so it resides here. This especially applies
to assembly/disassembly where parsing/printing can be quite involved.
Such things aren't really part of the specification of the cpu, per se,
so .cpu files provide the general framework and .opc files handle the
nitty-gritty details as necessary.
Each section is delimited with start and end markers.
<arch>-opc.h additions use: "-- opc.h"
<arch>-opc.c additions use: "-- opc.c"
<arch>-asm.c additions use: "-- asm.c"
<arch>-dis.c additions use: "-- dis.c"
<arch>-ibd.h additions use: "-- ibd.h"
*/
/* -- opc.h */
/* Allows reason codes to be output when assembler errors occur. */
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
/* Override disassembly hashing - there are variable bits in the top
byte of these instructions. */
#define CGEN_DIS_HASH_SIZE 8
#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE)
/* following activates check beyond hashing since some iq2000 and iq10
instructions have same mnemonics but different functionality. */
#define CGEN_VALIDATE_INSN_SUPPORTED
extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn);
/* -- asm.c */
static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_imm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
/* Special check to ensure that instruction exists for given machine. */
int
iq2000_cgen_insn_supported (cd, insn)
CGEN_CPU_DESC cd;
const CGEN_INSN *insn;
{
int machs = cd->machs;
return ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0);
}
static int iq2000_cgen_isa_register (strp)
const char **strp;
{
int len;
int ch1, ch2;
if (**strp == 'r' || **strp == 'R')
{
len = strlen (*strp);
if (len == 2)
{
ch1 = (*strp)[1];
if ('0' <= ch1 && ch1 <= '9')
return 1;
}
else if (len == 3)
{
ch1 = (*strp)[1];
ch2 = (*strp)[2];
if (('1' <= ch1 && ch1 <= '2') && ('0' <= ch2 && ch2 <= '9'))
return 1;
if ('3' == ch1 && (ch2 == '0' || ch2 == '1'))
return 1;
}
}
if (**strp == '%' && tolower((*strp)[1]) != 'l' && tolower((*strp)[1]) != 'h')
return 1;
return 0;
}
/* Handle negated literal. */
static const char *
parse_mimm (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
{
const char *errmsg;
long value;
/* Verify this isn't a register */
if (iq2000_cgen_isa_register (strp))
errmsg = _("immediate value cannot be register");
else
{
long value;
errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
if (errmsg == NULL)
{
long x = (-value) & 0xFFFF0000;
if (x != 0 && x != 0xFFFF0000)
errmsg = _("immediate value out of range");
else
*valuep = (-value & 0xFFFF);
}
}
return errmsg;
}
/* Handle signed/unsigned literal. */
static const char *
parse_imm (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
{
const char *errmsg;
long value;
if (iq2000_cgen_isa_register (strp))
errmsg = _("immediate value cannot be register");
else
{
long value;
errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
if (errmsg == NULL)
{
long x = value & 0xFFFF0000;
if (x != 0 && x != 0xFFFF0000)
errmsg = _("immediate value out of range");
else
*valuep = (value & 0xFFFF);
}
}
return errmsg;
}
/* Handle iq10 21-bit jmp offset. */
static const char *
parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
int reloc;
enum cgen_parse_operand_result *type_addr;
bfd_vma *valuep;
{
const char *errmsg;
bfd_vma value;
enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21,
&result_type, &value);
if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
/* Check value is within 23-bits (remembering that 2-bit shift right will occur). */
if (value > 0x7fffff)
return _("21-bit offset out of range");
}
*valuep = (value & 0x7FFFFF);
return errmsg;
}
/* Handle high(). */
static const char *
parse_hi16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
{
if (strncasecmp (*strp, "%hi(", 4) == 0)
{
enum cgen_parse_operand_result result_type;
bfd_vma value;
const char *errmsg;
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
&result_type, &value);
if (**strp != ')')
return _("missing `)'");
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
/* if value has top-bit of %lo on, then it will
sign-propagate and so we compensate by adding
1 to the resultant %hi value */
if (value & 0x8000)
value += 0x10000;
value >>= 16;
}
*valuep = value;
return errmsg;
}
/* we add %uhi in case a user just wants the high 16-bits or is using
an insn like ori for %lo which does not sign-propagate */
if (strncasecmp (*strp, "%uhi(", 5) == 0)
{
enum cgen_parse_operand_result result_type;
bfd_vma value;
const char *errmsg;
*strp += 5;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16,
&result_type, &value);
if (**strp != ')')
return _("missing `)'");
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
value >>= 16;
}
*valuep = value;
return errmsg;
}
return parse_imm (cd, strp, opindex, valuep);
}
/* Handle %lo in a signed context.
The signedness of the value doesn't matter to %lo(), but this also
handles the case where %lo() isn't present. */
static const char *
parse_lo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
{
if (strncasecmp (*strp, "%lo(", 4) == 0)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
&result_type, &value);
if (**strp != ')')
return _("missing `)'");
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
return parse_imm (cd, strp, opindex, valuep);
}
/* Handle %lo in a negated signed context.
The signedness of the value doesn't matter to %lo(), but this also
handles the case where %lo() isn't present. */
static const char *
parse_mlo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
{
if (strncasecmp (*strp, "%lo(", 4) == 0)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
&result_type, &value);
if (**strp != ')')
return _("missing `)'");
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (-value) & 0xffff;
*valuep = value;
return errmsg;
}
return parse_mimm (cd, strp, opindex, valuep);
}
/* -- */

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; IQ2000-only CPU description. -*- Scheme -*-
;
; Copyright 2000, 2001, 2002, 2004 Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc; developed under contract from Vitesse.
;
; This file is part of the GNU Binutils.
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
(dni andoui "and upper ones immediate" (MACH2000 USES-RS USES-RT)
"andoui $rt,$rs,$hi16"
(+ OP_ANDOUI rs rt hi16)
(set rt (and rs (or (sll hi16 16) #xFFFF)))
())
(dni andoui2 "and upper ones immediate" (ALIAS NO-DIS MACH2000 USES-RS USES-RT)
"andoui ${rt-rs},$hi16"
(+ OP_ANDOUI rt-rs hi16)
(set rt-rs (and rt-rs (or (sll hi16 16) #xFFFF)))
())
(dni orui2 "or upper immediate" (ALIAS NO-DIS MACH2000 USES-RS USES-RT)
"orui ${rt-rs},$hi16"
(+ OP_ORUI rt-rs hi16)
(set rt-rs (or rt-rs (sll hi16 16)))
())
(dni orui "or upper immediate" (MACH2000 USES-RS USES-RT)
"orui $rt,$rs,$hi16"
(+ OP_ORUI rs rt hi16)
(set rt (or rs (sll hi16 16)))
())
(dni bgtz "branch if greater than zero" (MACH2000 USES-RS)
"bgtz $rs,$offset"
(+ OP_BGTZ rs (f-rt 0) offset)
(if (gt rs 0)
(delay 1 (set pc offset)))
())
(dni bgtzl "branch if greater than zero likely" (MACH2000 USES-RS)
"bgtzl $rs,$offset"
(+ OP_BGTZL rs (f-rt 0) offset)
(if (gt rs 0)
(delay 1 (set pc offset))
(skip 1))
())
(dni blez "branch if less than or equal to zero" (MACH2000 USES-RS)
"blez $rs,$offset"
(+ OP_BLEZ rs (f-rt 0) offset)
(if (le rs 0)
(delay 1 (set pc offset)))
())
(dni blezl "branch if less than or equal to zero likely" (MACH2000 USES-RS)
"blezl $rs,$offset"
(+ OP_BLEZL rs (f-rt 0) offset)
(if (le rs 0)
(delay 1 (set pc offset))
(skip 1))
())
(dni mrgb "merge bytes" (MACH2000 USES-RD USES-RS USES-RT)
"mrgb $rd,$rs,$rt,$mask"
(+ OP_SPECIAL rs rt rd (f-10 0) mask FUNC_MRGB)
(sequence ((SI temp))
(if (bitclear? mask 0)
(set temp (and rs #xFF))
(set temp (and rt #xFF)))
(if (bitclear? mask 1)
(set temp (or temp (and rs #xFF00)))
(set temp (or temp (and rt #xFF00))))
(if (bitclear? mask 2)
(set temp (or temp (and rs #xFF0000)))
(set temp (or temp (and rt #xFF0000))))
(if (bitclear? mask 3)
(set temp (or temp (and rs #xFF000000)))
(set temp (or temp (and rt #xFF000000))))
(set rd temp))
())
(dni mrgb2 "merge bytes" (ALIAS NO-DIS MACH2000 USES-RD USES-RS USES-RT)
"mrgb ${rd-rs},$rt,$mask"
(+ OP_SPECIAL rt rd-rs (f-10 0) mask FUNC_MRGB)
(sequence ((SI temp))
(if (bitclear? mask 0)
(set temp (and rd-rs #xFF))
(set temp (and rt #xFF)))
(if (bitclear? mask 1)
(set temp (or temp (and rd-rs #xFF00)))
(set temp (or temp (and rt #xFF00))))
(if (bitclear? mask 2)
(set temp (or temp (and rd-rs #xFF0000)))
(set temp (or temp (and rt #xFF0000))))
(if (bitclear? mask 3)
(set temp (or temp (and rd-rs #xFF000000)))
(set temp (or temp (and rt #xFF000000))))
(set rd-rs temp))
())
; NOTE: None of these instructions' semantics are specified, so they
; will not work in a simulator.
;
; Architectural and coprocessor instructions.
; BREAK and SYSCALL are implemented with escape hatches to the C
; code. These are used by the test suite to indicate pass/failures.
(dni bctxt "branch and switch context" (MACH2000 DELAY-SLOT COND-CTI USES-RS)
"bctxt $rs,$offset"
(+ OP_REGIMM rs (f-rt 6) offset)
(unimp bctxt)
())
(dni bc0f "branch if copro 0 condition false" (MACH2000 DELAY-SLOT COND-CTI)
"bc0f $offset"
(+ OP_COP0 (f-rs 8) (f-rt 0) offset)
(unimp bc0f)
())
(dni bc0fl "branch if copro 0 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
"bc0fl $offset"
(+ OP_COP0 (f-rs 8) (f-rt 2) offset)
(unimp bc0fl)
())
(dni bc3f "branch if copro 3 condition false" (MACH2000 DELAY-SLOT COND-CTI)
"bc3f $offset"
(+ OP_COP3 (f-rs 8) (f-rt 0) offset)
(unimp bc3f)
())
(dni bc3fl "branch if copro 3 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
"bc3fl $offset"
(+ OP_COP3 (f-rs 8) (f-rt 2) offset)
(unimp bc3fl)
())
(dni bc0t "branch if copro 0 condition true" (MACH2000 DELAY-SLOT COND-CTI)
"bc0t $offset"
(+ OP_COP0 (f-rs 8) (f-rt 1) offset)
(unimp bc0t)
())
(dni bc0tl "branch if copro 0 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
"bc0tl $offset"
(+ OP_COP0 (f-rs 8) (f-rt 3) offset)
(unimp bc0tl)
())
(dni bc3t "branch if copro 3 condition true" (MACH2000 DELAY-SLOT COND-CTI)
"bc3t $offset"
(+ OP_COP3 (f-rs 8) (f-rt 1) offset)
(unimp bc3t)
())
(dni bc3tl "branch if copro 3 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
"bc3tl $offset"
(+ OP_COP3 (f-rs 8) (f-rt 3) offset)
(unimp bc3tl)
())
; Note that we don't set the USES-RD or USES-RT attributes for many of the following
; instructions, as it's the COP register that's being specified.
(dni cfc0 "control from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
"cfc0 $rt,$rd"
(+ OP_COP0 (f-rs 2) rt rd (f-10-11 0))
(unimp cfc0)
())
(dni cfc1 "control from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT)
"cfc1 $rt,$rd"
(+ OP_COP1 (f-rs 2) rt rd (f-10-11 0))
(unimp cfc1)
())
(dni cfc2 "control from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
"cfc2 $rt,$rd"
(+ OP_COP2 (f-rs 2) rt rd (f-10-11 0))
(unimp cfc2)
())
(dni cfc3 "control from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
"cfc3 $rt,$rd"
(+ OP_COP3 (f-rs 2) rt rd (f-10-11 0))
(unimp cfc3)
())
; COPz instructions are an instruction form, not real instructions
; with associated assembly mnemonics. Therefore, they are omitted
; from the ISA description.
(dni chkhdr "check header" (MACH2000 LOAD-DELAY USES-RD YIELD-INSN)
"chkhdr $rd,$rt"
(+ OP_COP3 (f-rs 9) rt rd (f-shamt 0) (f-func 0))
(unimp chkhdr)
())
(dni ctc0 "control to coprocessor 0" (MACH2000 USES-RT)
"ctc0 $rt,$rd"
(+ OP_COP0 (f-rs 6) rt rd (f-10-11 0))
(unimp ctc0)
())
(dni ctc1 "control to coprocessor 1" (MACH2000 USES-RT)
"ctc1 $rt,$rd"
(+ OP_COP1 (f-rs 6) rt rd (f-10-11 0))
(unimp ctc1)
())
(dni ctc2 "control to coprocessor 2" (MACH2000 USES-RT)
"ctc2 $rt,$rd"
(+ OP_COP2 (f-rs 6) rt rd (f-10-11 0))
(unimp ctc2)
())
(dni ctc3 "control to coprocessor 3" (MACH2000 USES-RT)
"ctc3 $rt,$rd"
(+ OP_COP3 (f-rs 6) rt rd (f-10-11 0))
(unimp ctc3)
())
(dni jcr "jump context register" (MACH2000 DELAY-SLOT UNCOND-CTI USES-RS)
"jcr $rs"
(+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JCR)
(unimp jcr)
())
(dni luc32 "lookup chain 32 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
"luc32 $rt,$rd"
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 3))
(unimp luc32)
())
(dni luc32l "lookup chain 32 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
"luc32l $rt,$rd"
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 7))
(unimp luc32l)
())
(dni luc64 "lookup chain 64 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
"luc64 $rt,$rd"
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 11))
(unimp luc64)
())
(dni luc64l "lookup chain 64 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
"luc64l $rt,$rd"
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 15))
(unimp luc64l)
())
(dni luk "lookup key" (MACH2000 USES-RD USES-RT)
"luk $rt,$rd"
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 8))
(unimp luk)
())
(dni lulck "lookup lock" (MACH2000 USES-RT YIELD-INSN)
"lulck $rt"
(+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 4))
(unimp lulck)
())
(dni lum32 "lookup match 32 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
"lum32 $rt,$rd"
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 2))
(unimp lum32)
())
(dni lum32l "lookup match 32 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
"lum32l $rt,$rd"
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 6))
(unimp lum32l)
())
(dni lum64 "lookup match 64 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
"lum64 $rt,$rd"
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 10))
(unimp lum64)
())
(dni lum64l "lookup match 64 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
"lum64l $rt,$rd"
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 14))
(unimp lum64l)
())
(dni lur "lookup read" (MACH2000 USES-RD USES-RT YIELD-INSN)
"lur $rt,$rd"
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 1))
(unimp lur)
())
(dni lurl "lookup read and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
"lurl $rt,$rd"
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 5))
(unimp lurl)
())
(dni luulck "lookup unlock" (MACH2000 USES-RT YIELD-INSN)
"luulck $rt"
(+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 0))
(unimp luulck)
())
(dni mfc0 "move from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
"mfc0 $rt,$rd"
(+ OP_COP0 (f-rs 0) rt rd (f-10-11 0))
(unimp mfc0)
())
(dni mfc1 "move from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT)
"mfc1 $rt,$rd"
(+ OP_COP1 (f-rs 0) rt rd (f-10-11 0))
(unimp mfc1)
())
(dni mfc2 "move from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
"mfc2 $rt,$rd"
(+ OP_COP2 (f-rs 0) rt rd (f-10-11 0))
(unimp mfc2)
())
(dni mfc3 "move from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
"mfc3 $rt,$rd"
(+ OP_COP3 (f-rs 0) rt rd (f-10-11 0))
(unimp mfc3)
())
(dni mtc0 "move to coprocessor 0" (MACH2000 USES-RT)
"mtc0 $rt,$rd"
(+ OP_COP0 (f-rs 4) rt rd (f-10-11 0))
(unimp mtc0)
())
(dni mtc1 "move to coprocessor 1" (MACH2000 USES-RT)
"mtc1 $rt,$rd"
(+ OP_COP1 (f-rs 4) rt rd (f-10-11 0))
(unimp mtc1)
())
(dni mtc2 "move to coprocessor 2" (MACH2000 USES-RT)
"mtc2 $rt,$rd"
(+ OP_COP2 (f-rs 4) rt rd (f-10-11 0))
(unimp mtc2)
())
(dni mtc3 "move to coprocessor 3" (MACH2000 USES-RT)
"mtc3 $rt,$rd"
(+ OP_COP3 (f-rs 4) rt rd (f-10-11 0))
(unimp mtc3)
())
(dni pkrl "pkrl" (MACH2000 USES-RD USES-RT YIELD-INSN)
"pkrl $rd,$rt"
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 7))
(unimp pkrl)
())
(dni pkrlr1 "pkrlr1" (MACH2000 USES-RT YIELD-INSN)
"pkrlr1 $rt,$_index,$count"
(+ OP_COP3 (f-rs 29) rt count _index)
(unimp pkrlr1)
())
(dni pkrlr30 "pkrlr30" (MACH2000 USES-RT YIELD-INSN)
"pkrlr30 $rt,$_index,$count"
(+ OP_COP3 (f-rs 31) rt count _index)
(unimp pkrlr30)
())
(dni rb "dma read bytes" (MACH2000 USES-RD USES-RT YIELD-INSN)
"rb $rd,$rt"
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 4))
(unimp rb)
())
(dni rbr1 "dma read bytes using r1" (MACH2000 USES-RT YIELD-INSN)
"rbr1 $rt,$_index,$count"
(+ OP_COP3 (f-rs 24) rt count _index)
(unimp rbr1)
())
(dni rbr30 "dma read bytes using r30" (MACH2000 USES-RT YIELD-INSN)
"rbr30 $rt,$_index,$count"
(+ OP_COP3 (f-rs 26) rt count _index)
(unimp rbr30)
())
(dni rfe "restore from exception" (MACH2000)
"rfe"
(+ OP_COP0 (f-25 1) (f-24-19 0) (f-func 16))
(unimp rfe)
())
(dni rx "dma read word64s" (MACH2000 USES-RD USES-RT YIELD-INSN)
"rx $rd,$rt"
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 6))
(unimp rx)
())
(dni rxr1 "dma read word64s using r1" (MACH2000 USES-RT YIELD-INSN)
"rxr1 $rt,$_index,$count"
(+ OP_COP3 (f-rs 28) rt count _index)
(unimp rxr1)
())
(dni rxr30 "dma read word 64s using r30" (MACH2000 USES-RT YIELD-INSN)
"rxr30 $rt,$_index,$count"
(+ OP_COP3 (f-rs 30) rt count _index)
(unimp rxr30)
())
(dni sleep "sleep" (MACH2000 YIELD-INSN)
"sleep"
(+ OP_SPECIAL execode FUNC_SLEEP)
(unimp sleep)
())
(dni srrd "sram read" (MACH2000 USES-RT YIELD-INSN)
"srrd $rt"
(+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 16))
(unimp srrd)
())
(dni srrdl "sram read and lock" (MACH2000 USES-RT YIELD-INSN)
"srrdl $rt"
(+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 20))
(unimp srrdl)
())
(dni srulck "sram unlock" (MACH2000 USES-RT YIELD-INSN)
"srulck $rt"
(+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 22))
(unimp srulck)
())
(dni srwr "sram write" (MACH2000 USES-RD USES-RT YIELD-INSN)
"srwr $rt,$rd"
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 17))
(unimp srwr)
())
(dni srwru "sram write and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN)
"srwru $rt,$rd"
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 21))
(unimp srwru)
())
(dni trapqfl "yield if dma queue full" (MACH2000 YIELD-INSN)
"trapqfl"
(+ OP_COP3 (f-rs 1) (f-rt 0) (f-rd 0) (f-shamt 0) (f-func 8))
(unimp trapqfl)
())
(dni trapqne "yield if dma queue not empty" (MACH2000 YIELD-INSN)
"trapqne"
(+ OP_COP3 (f-rs 1) (f-rt 0) (f-rd 0) (f-shamt 0) (f-func 9))
(unimp trapqne)
())
(dni traprel "traprel" (MACH2000 USES-RT YIELD-INSN)
"traprel $rt"
(+ OP_COP3 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 10))
(unimp traprel)
())
(dni wb "dma write bytes" (MACH2000 USES-RD USES-RT YIELD-INSN)
"wb $rd,$rt"
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 0))
(unimp wb)
())
(dni wbu "dma write bytes and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN)
"wbu $rd,$rt"
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 1))
(unimp wbu)
())
(dni wbr1 "dma write bytes using r1" (MACH2000 USES-RT YIELD-INSN)
"wbr1 $rt,$_index,$count"
(+ OP_COP3 (f-rs 16) rt count _index)
(unimp wbr1)
())
(dni wbr1u "dma write bytes using r1 and unlock" (MACH2000 USES-RT YIELD-INSN)
"wbr1u $rt,$_index,$count"
(+ OP_COP3 (f-rs 17) rt count _index)
(unimp wbr1u)
())
(dni wbr30 "dma write bytes using r30" (MACH2000 USES-RT YIELD-INSN)
"wbr30 $rt,$_index,$count"
(+ OP_COP3 (f-rs 18) rt count _index)
(unimp wbr30)
())
(dni wbr30u "dma write bytes using r30 and unlock" (MACH2000 USES-RT YIELD-INSN)
"wbr30u $rt,$_index,$count"
(+ OP_COP3 (f-rs 19) rt count _index)
(unimp wbr30u)
())
(dni wx "dma write word64s" (MACH2000 USES-RD USES-RT YIELD-INSN)
"wx $rd,$rt"
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 2))
(unimp wx)
())
(dni wxu "dma write word64s and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN)
"wxu $rd,$rt"
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 3))
(unimp wxu)
())
(dni wxr1 "dma write word64s using r1" (MACH2000 USES-RT YIELD-INSN)
"wxr1 $rt,$_index,$count"
(+ OP_COP3 (f-rs 20) rt count _index)
(unimp wxr1)
())
(dni wxr1u "dma write word64s using r1 and unlock" (MACH2000 USES-RT YIELD-INSN)
"wxr1u $rt,$_index,$count"
(+ OP_COP3 (f-rs 21) rt count _index)
(unimp wxr1u)
())
(dni wxr30 "dma write word64s using r30" (MACH2000 USES-RT YIELD-INSN)
"wxr30 $rt,$_index,$count"
(+ OP_COP3 (f-rs 22) rt count _index)
(unimp wxr30)
())
(dni wxr30u "dma write word64s using r30 and unlock" (MACH2000 USES-RT YIELD-INSN)
"wxr30u $rt,$_index,$count"
(+ OP_COP3 (f-rs 23) rt count _index)
(unimp wxr30u)
())
; Load/Store instructions.
(dni ldw "load double word" (MACH2000 EVEN-REG-NUM LOAD-DELAY USES-RT)
"ldw $rt,$lo16($base)"
(+ OP_LDW base rt lo16)
(sequence ((SI addr))
(set addr (and (add base lo16) (inv 3)))
(set (reg h-gr (add (ifield f-rt) 1)) (mem SI addr))
(set rt (mem SI (add addr 4))))
())
(dni sdw "store double word" (MACH2000 EVEN-REG-NUM USES-RT)
"sdw $rt,$lo16($base)"
(+ OP_SDW base rt lo16)
(sequence ((SI addr))
(set addr (and (add base lo16) (inv 3)))
(set (mem SI (add addr 4)) rt)
(set (mem SI addr) (reg h-gr (add (ifield f-rt) 1))))
())
; Jump instructions
(dni j "jump" (MACH2000)
"j $jmptarg"
(+ OP_J (f-rsrvd 0) jmptarg)
(delay 1 (set pc jmptarg))
())
(dni jal "jump and link" (MACH2000 USES-R31)
"jal $jmptarg"
(+ OP_JAL (f-rsrvd 0) jmptarg)
(delay 1
(sequence ()
(set (reg h-gr 31) (add pc 8))
(set pc jmptarg)))
())
(dni bmb "branch if matching byte-lane" (MACH2000 USES-RS USES-RT)
"bmb $rs,$rt,$offset"
(+ OP_BMB rs rt offset)
(sequence ((BI branch?))
(set branch? 0)
(if (eq (and rs #xFF) (and rt #xFF))
(set branch? 1))
(if (eq (and rs #xFF00) (and rt #xFF00))
(set branch? 1))
(if (eq (and rs #xFF0000) (and rt #xFF0000))
(set branch? 1))
(if (eq (and rs #xFF000000) (and rt #xFF000000))
(set branch? 1))
(if branch?
(delay 1 (set pc offset))))
())
; Macros
(dnmi ldw-base-0 "load double word - implied base 0" (MACH2000 EVEN-REG-NUM LOAD-DELAY USES-RT USES-RS NO-DIS)
"ldw $rt,$lo16"
(emit ldw rt lo16 (base 0))
)
(dnmi sdw-base-0 "store double word - implied base 0" (MACH2000 EVEN-REG-NUM USES-RT NO-DIS)
"sdw $rt,$lo16"
(emit sdw rt lo16 (base 0))
)

2426
binutils/cpu/m32r.cpu Normal file
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343
binutils/cpu/m32r.opc Normal file
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@@ -0,0 +1,343 @@
/* M32R opcode support. -*- C -*-
Copyright 1998, 1999, 2000, 2001, 2004, 2005
Free Software Foundation, Inc.
Contributed by Red Hat Inc; developed under contract from
Mitsubishi Electric Corporation.
This file is part of the GNU Binutils.
Contributed by Red Hat Inc; developed under contract from Fujitsu.
This file is part of the GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* This file is an addendum to m32r.cpu. Heavy use of C code isn't
appropriate in .cpu files, so it resides here. This especially applies
to assembly/disassembly where parsing/printing can be quite involved.
Such things aren't really part of the specification of the cpu, per se,
so .cpu files provide the general framework and .opc files handle the
nitty-gritty details as necessary.
Each section is delimited with start and end markers.
<arch>-opc.h additions use: "-- opc.h"
<arch>-opc.c additions use: "-- opc.c"
<arch>-asm.c additions use: "-- asm.c"
<arch>-dis.c additions use: "-- dis.c"
<arch>-ibd.h additions use: "-- ibd.h" */
/* -- opc.h */
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 256
#undef CGEN_DIS_HASH
#if 0
#define X(b) (((unsigned char *) (b))[0] & 0xf0)
#define CGEN_DIS_HASH(buffer, value) \
(X (buffer) | \
(X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
: X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
: X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
: ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
#else
#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value)
extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT);
#endif
/* -- */
/* -- opc.c */
unsigned int
m32r_cgen_dis_hash (buf, value)
const char * buf ATTRIBUTE_UNUSED;
CGEN_INSN_INT value;
{
unsigned int x;
if (value & 0xffff0000) /* 32bit instructions */
value = (value >> 16) & 0xffff;
x = (value>>8) & 0xf0;
if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
return x;
if (x == 0x70 || x == 0xf0)
return x | ((value>>8) & 0x0f);
if (x == 0x30)
return x | ((value & 0x70) >> 4);
else
return x | ((value & 0xf0) >> 4);
}
/* -- */
/* -- asm.c */
static const char * parse_hash
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_hi16
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_slo16
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_ulo16
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
/* Handle '#' prefixes (i.e. skip over them). */
static const char *
parse_hash (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
const char **strp;
int opindex ATTRIBUTE_UNUSED;
long *valuep ATTRIBUTE_UNUSED;
{
if (**strp == '#')
++*strp;
return NULL;
}
/* Handle shigh(), high(). */
static const char *
parse_hi16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
if (**strp == '#')
++*strp;
if (strncasecmp (*strp, "high(", 5) == 0)
{
*strp += 5;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO,
&result_type, &value);
if (**strp != ')')
return "missing `)'";
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value >>= 16;
*valuep = value;
return errmsg;
}
else if (strncasecmp (*strp, "shigh(", 6) == 0)
{
*strp += 6;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO,
&result_type, &value);
if (**strp != ')')
return "missing `)'";
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
value = value + (value & 0x8000 ? 0x10000 : 0);
value >>= 16;
}
*valuep = value;
return errmsg;
}
return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
}
/* Handle low() in a signed context. Also handle sda().
The signedness of the value doesn't matter to low(), but this also
handles the case where low() isn't present. */
static const char *
parse_slo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
if (**strp == '#')
++*strp;
if (strncasecmp (*strp, "low(", 4) == 0)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
&result_type, &value);
if (**strp != ')')
return "missing `)'";
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
value &= 0xffff;
if (value & 0x8000)
value |= 0xffff0000;
}
*valuep = value;
return errmsg;
}
if (strncasecmp (*strp, "sda(", 4) == 0)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16,
NULL, &value);
if (**strp != ')')
return "missing `)'";
++*strp;
*valuep = value;
return errmsg;
}
return cgen_parse_signed_integer (cd, strp, opindex, valuep);
}
/* Handle low() in an unsigned context.
The signedness of the value doesn't matter to low(), but this also
handles the case where low() isn't present. */
static const char *
parse_ulo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
if (**strp == '#')
++*strp;
if (strncasecmp (*strp, "low(", 4) == 0)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
&result_type, &value);
if (**strp != ')')
return "missing `)'";
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
*valuep = value;
return errmsg;
}
return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
}
/* -- */
/* -- dis.c */
static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
/* Immediate values are prefixed with '#'. */
#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \
do \
{ \
if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \
(*info->fprintf_func) (info->stream, "#"); \
} \
while (0)
/* Handle '#' prefixes as operands. */
static void
print_hash (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value ATTRIBUTE_UNUSED;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "#");
}
#undef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN my_print_insn
static int
my_print_insn (cd, pc, info)
CGEN_CPU_DESC cd;
bfd_vma pc;
disassemble_info *info;
{
char buffer[CGEN_MAX_INSN_SIZE];
char *buf = buffer;
int status;
int buflen = (pc & 3) == 0 ? 4 : 2;
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
char *x;
/* Read the base part of the insn. */
status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) ? 2 : 0),
buf, buflen, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
return -1;
}
/* 32 bit insn? */
x = (big_p ? &buf[0] : &buf[3]);
if ((pc & 3) == 0 && (*x & 0x80) != 0)
return print_insn (cd, pc, info, buf, buflen);
/* Print the first insn. */
if ((pc & 3) == 0)
{
buf += (big_p ? 0 : 2);
if (print_insn (cd, pc, info, buf, 2) == 0)
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
buf += (big_p ? 2 : -2);
}
x = (big_p ? &buf[0] : &buf[1]);
if (*x & 0x80)
{
/* Parallel. */
(*info->fprintf_func) (info->stream, " || ");
*x &= 0x7f;
}
else
(*info->fprintf_func) (info->stream, " -> ");
/* The "& 3" is to pass a consistent address.
Parallel insns arguably both begin on the word boundary.
Also, branch insns are calculated relative to the word boundary. */
if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
return (pc & 3) ? 2 : 4;
}
/* -- */

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; Hitachi SH architecture description. -*- Scheme -*-
;
; Copyright 2000, 2001 Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc; developed under contract from Hitachi
; Semiconductor (America) Inc.
;
; This file is part of the GNU Binutils.
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
(include "simplify.inc")
(define-arch
(name sh)
(comment "Hitachi SuperH (SH)")
(insn-lsb0? #t)
(machs sh2 sh3 sh3e sh4 sh5)
(isas compact media)
)
; Instruction sets.
(define-isa
(name media)
(comment "SHmedia 32-bit instruction set")
(base-insn-bitsize 32)
)
(define-isa
(name compact)
(comment "SHcompact 16-bit instruction set")
(base-insn-bitsize 16)
)
; CPU family.
(define-cpu
(name sh64)
(comment "SH 64-bit family")
(endian either)
(word-bitsize 32)
)
(define-mach
(name sh2)
(comment "SH-2 CPU core")
(cpu sh64)
(isas compact)
)
(define-mach
(name sh3)
(comment "SH-3 CPU core")
(cpu sh64)
(isas compact)
)
(define-mach
(name sh3e)
(comment "SH-3e CPU core")
(cpu sh64)
(isas compact)
)
(define-mach
(name sh4)
(comment "SH-4 CPU core")
(cpu sh64)
(isas compact)
)
(define-mach
(name sh5)
(comment "SH-5 CPU core")
(cpu sh64)
(isas compact media)
)
(define-model
(name sh5)
(comment "SH-5 reference implementation")
(mach sh5)
(unit u-exec "Execution unit" ()
1 1 ; issue done
() () () ())
)
; Hardware elements.
(define-hardware
(name h-pc)
(comment "Program counter")
(attrs PC (ISA compact,media))
(type pc UDI)
(get () (raw-reg h-pc))
(set (newval) (sequence ()
(set (raw-reg h-ism) (and newval 1))
(set (raw-reg h-pc) (and newval (inv UDI 1)))))
)
(define-pmacro (-build-greg-name n) ((.sym r n) n))
(define-hardware
(name h-gr)
(comment "General purpose integer registers")
(attrs (ISA media,compact))
(type register DI (64))
(indices keyword "" (.map -build-greg-name (.iota 64)))
(get (index)
(if DI (eq index 63)
(const 0)
(raw-reg h-gr index)))
(set (index newval)
(if (ne index 63)
(set (raw-reg h-gr index) newval)
(nop)))
)
(define-hardware
(name h-grc)
(comment "General purpose integer registers (SHcompact view)")
(attrs VIRTUAL (ISA compact))
(type register SI (16))
(indices keyword "" (.map -build-greg-name (.iota 16)))
(get (index)
(and (raw-reg h-gr index) (zext DI #xFFFFFFFF)))
(set (index newval)
(set (raw-reg h-gr index) (ext DI newval)))
)
(define-pmacro (-build-creg-name n) ((.sym cr n) n))
(define-hardware
(name h-cr)
(comment "Control registers")
(attrs (ISA media))
(type register DI (64))
(indices keyword "" (.map -build-creg-name (.iota 64)))
(get (index)
(if DI (eq index 0)
(zext DI (reg h-sr))
(raw-reg h-cr index)))
(set (index newval)
(if (eq index 0)
(set (reg h-sr) newval)
(set (raw-reg h-cr index) newval)))
)
(define-hardware
(name h-sr)
(comment "Status register")
(attrs (ISA compact,media))
(type register SI)
)
(define-hardware
(name h-fpscr)
(comment "Floating point status and control register")
(attrs (ISA compact,media))
(type register SI)
)
(define-hardware
(name h-frbit)
(comment "Floating point register file bit")
(attrs (ISA media,compact) VIRTUAL)
(type register BI)
(get () (and (srl (reg h-sr) 14) 1))
(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 14))) (sll SI newvalue 14))))
)
(define-hardware
(name h-szbit)
(comment "Floating point transfer size bit")
(attrs (ISA media,compact) VIRTUAL)
(type register BI)
(get () (and (srl (reg h-sr) 13) 1))
(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 13))) (sll SI newvalue 13))))
)
(define-hardware
(name h-prbit)
(comment "Floating point precision bit")
(attrs (ISA media,compact) VIRTUAL)
(type register BI)
(get () (and (srl (reg h-sr) 12) 1))
(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 12))) (sll SI newvalue 12))))
)
(define-hardware
(name h-sbit)
(comment "Multiply-accumulate saturation flag")
(attrs (ISA compact) VIRTUAL)
(type register BI)
(get () (and (srl (reg h-sr) 1) 1))
(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv 2)) (sll SI newvalue 1))))
)
(define-hardware
(name h-mbit)
(comment "Divide-step M flag")
(attrs (ISA compact) VIRTUAL)
(type register BI)
(get () (and (srl (reg h-sr) 9) 1))
(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 9))) (sll SI newvalue 9))))
)
(define-hardware
(name h-qbit)
(comment "Divide-step Q flag")
(attrs (ISA compact) VIRTUAL)
(type register BI)
(get () (and (srl (reg h-sr) 8) 1))
(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 8))) (sll SI newvalue 8))))
)
(define-pmacro (-build-freg-name n) ((.sym fr n) n))
(define-hardware
(name h-fr)
(comment "Single precision floating point registers")
(attrs (ISA media,compact))
(type register SF (64))
(indices keyword "" (.map -build-freg-name (.iota 64)))
)
(define-pmacro (-build-fpair-name n) ((.sym fp n) n))
(define-hardware
(name h-fp)
(comment "Single precision floating point register pairs")
(attrs (ISA media,compact))
(type register DF (32))
(indices keyword "" (.map -build-fpair-name (.iota 32)))
)
(define-pmacro (-build-fvec-name n) ((.sym fv n) n))
(define-hardware
(name h-fv)
(comment "Single precision floating point vectors")
(attrs VIRTUAL (ISA media,compact))
(type register SF (16))
(indices keyword "" (.map -build-fvec-name (.iota 16)))
; Mask with $F to ensure 0 <= index < 15.
(get (index) (reg h-fr (mul (and UQI index 15) 4)))
(set (index newval) (set (reg h-fr (mul (and UQI index 15) 4)) newval))
)
(define-hardware
(name h-fmtx)
(comment "Single precision floating point matrices")
(attrs VIRTUAL (ISA media))
(type register SF (4))
(indices keyword "" ((mtrx0 0) (mtrx1 1) (mtrx2 2) (mtrx3 3)))
; Mask with $3 to ensure 0 <= index < 4.
(get (index) (reg h-fr (mul (and UQI index 3) 16)))
(set (index newval) (set (reg h-fr (mul (and UQI index 3) 16)) newval))
)
(define-pmacro (-build-dreg-name n) ((.sym dr n) n))
(define-hardware
(name h-dr)
(comment "Double precision floating point registers")
(attrs (ISA media,compact) VIRTUAL)
(type register DF (32))
(indices keyword "" (.map -build-dreg-name (.iota 64)))
(get (index)
(subword DF
(or
(sll DI (zext DI (subword SI (reg h-fr index) 0)) 32)
(zext DI (subword SI (reg h-fr (add index 1)) 0))) 0))
(set (index newval)
(sequence ()
(set (reg h-fr index)
(subword SF (subword SI newval 0) 0))
(set (reg h-fr (add index 1))
(subword SF (subword SI newval 1) 0))))
)
(define-hardware
(name h-tr)
(comment "Branch target registers")
(attrs (ISA media))
(type register DI (8))
(indices keyword "" ((tr0 0) (tr1 1) (tr2 2) (tr3 3) (tr4 4) (tr5 5) (tr6 6) (tr7 7)))
)
(define-hardware
(name h-endian)
(comment "Current endian mode")
(attrs (ISA compact,media) VIRTUAL)
(type register BI)
(get () (c-call BI "sh64_endian"))
(set (newval) (error "cannot alter target byte order mid-program"))
)
(define-hardware
(name h-ism)
(comment "Current instruction set mode")
(attrs (ISA compact,media))
(type register BI)
(get () (raw-reg h-ism))
(set (newval) (error "cannot set ism directly"))
)
; Operands.
(dnop endian "Endian mode" ((ISA compact,media)) h-endian f-nil)
(dnop ism "Instruction set mode" ((ISA compact,media)) h-ism f-nil)
; Universally useful macros.
; A pmacro for use in semantic bodies of unimplemented insns.
(define-pmacro (unimp mnemonic) (nop))
; Join 2 ints together in natural bit order.
(define-pmacro (-join-si s1 s0)
(or (sll (zext DI s1) 32)
(zext DI s0)))
; Join 4 half-ints together in natural bit order.
(define-pmacro (-join-hi h3 h2 h1 h0)
(or (sll (zext DI h3) 48)
(or (sll (zext DI h2) 32)
(or (sll (zext DI h1) 16)
(zext DI h0)))))
; Join 8 quarter-ints together in natural bit order.
(define-pmacro (-join-qi b7 b6 b5 b4 b3 b2 b1 b0)
(or (sll (zext DI b7) 56)
(or (sll (zext DI b6) 48)
(or (sll (zext DI b5) 40)
(or (sll (zext DI b4) 32)
(or (sll (zext DI b3) 24)
(or (sll (zext DI b2) 16)
(or (sll (zext DI b1) 8)
(zext DI b0)))))))))
; Include the two instruction set descriptions from their respective
; source files.
(if (keep-isa? (compact))
(include "sh64-compact.cpu"))
(if (keep-isa? (media))
(include "sh64-media.cpu"))

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/* SHmedia opcode support. -*- C -*-
Copyright 2000 Free Software Foundation, Inc.
Contributed by Red Hat Inc; developed under contract from Hitachi
Semiconductor (America) Inc.
This file is part of the GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* This file is an addendum to sh-media.cpu. Heavy use of C code isn't
appropriate in .cpu files, so it resides here. This especially applies
to assembly/disassembly where parsing/printing can be quite involved.
Such things aren't really part of the specification of the cpu, per se,
so .cpu files provide the general framework and .opc files handle the
nitty-gritty details as necessary.
Each section is delimited with start and end markers.
<arch>-opc.h additions use: "-- opc.h"
<arch>-opc.c additions use: "-- opc.c"
<arch>-asm.c additions use: "-- asm.c"
<arch>-dis.c additions use: "-- dis.c"
<arch>-ibd.h additions use: "-- ibd.h"
*/
/* -- opc.h */
/* Allows reason codes to be output when assembler errors occur. */
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
/* Override disassembly hashing - there are variable bits in the top
byte of these instructions. */
#define CGEN_DIS_HASH_SIZE 8
#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE)
/* -- asm.c */
static const char *
parse_fsd (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
{
abort();
}
/* -- dis.c */
static void
print_likely (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd;
PTR dis_info;
long value;
unsigned int attrs;
bfd_vma pc;
int length;
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, (value) ? "/l" : "/u");
}
/* -- */

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binutils/cpu/simplify.inc Normal file
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; Collection of macros, for GNU Binutils .cpu files. -*- Scheme -*-
;
; Copyright 2000 Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc.
;
; This file is part of the GNU Binutils.
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
; Enums.
; Define a normal enum without using name/value pairs.
; This is currently the same as define-full-enum but it needn't remain
; that way (it's define-full-enum that would change).
(define-pmacro (define-normal-enum name comment attrs prefix vals)
"\
Define a normal enum, fixed number of arguments.
"
(define-full-enum name comment attrs prefix vals)
)
; Define a normal insn enum.
(define-pmacro (define-normal-insn-enum name comment attrs prefix fld vals)
"\
Define a normal instruction opcode enum.
"
(define-full-insn-enum name comment attrs prefix fld vals)
)
; Instruction fields.
; Normally, fields are unsigned have no encode/decode needs.
(define-pmacro (define-normal-ifield name comment attrs start length)
"Define a normal instruction field.\n"
(define-full-ifield name comment attrs start length UINT #f #f)
)
; For those who don't like typing.
(define-pmacro df
"Shorthand form of define-full-ifield.\n"
define-full-ifield
)
(define-pmacro dnf
"Shorthand form of define-normal-ifield.\n"
define-normal-ifield
)
; Define a normal multi-ifield.
; FIXME: The define-normal version for ifields doesn't include the mode.
(define-pmacro (define-normal-multi-ifield name comment attrs
mode subflds insert extract)
"Define a normal multi-part instruction field.\n"
(define-full-multi-ifield name comment attrs mode subflds insert extract)
)
; For those who don't like typing.
(define-pmacro dnmf
"Shorthand form of define-normal-multi-ifield.\n"
define-normal-multi-ifield
)
; Simple multi-ifields: mode is UINT, default insert/extract support.
(define-pmacro (dsmf name comment attrs subflds)
"Define a simple multi-part instruction field.\n"
(define-full-multi-ifield name comment attrs UINT subflds #f #f)
)
; Hardware.
; Simpler version for most hardware elements.
; Allow special assembler support specification but no semantic-name or
; get/set specs.
(define-pmacro (define-normal-hardware name comment attrs type
indices values handlers)
"\
Define a normal hardware element.
"
(define-full-hardware name comment attrs name type
indices values handlers () () ())
)
; For those who don't like typing.
(define-pmacro dnh
"Shorthand form of define-normal-hardware.\n"
define-normal-hardware
)
; Simpler version of dnh that leaves out the indices, values, handlers,
; get, set, and layout specs.
; This is useful for 1 bit registers.
; ??? While dsh and dnh aren't that distinguishable when perusing a .cpu file,
; they both take a fixed number of positional arguments, and dsh is a proper
; subset of dnh with all arguments in the same positions, so methinks things
; are ok.
(define-pmacro (define-simple-hardware name comment attrs type)
"\
Define a simple hardware element (usually a scalar register).
"
(define-full-hardware name comment attrs name type () () () () () ())
)
(define-pmacro dsh
"Shorthand form of define-simple-hardware.\n"
define-simple-hardware
)
; Operands.
(define-pmacro (define-normal-operand name comment attrs type index)
"Define a normal operand.\n"
(define-full-operand name comment attrs type DFLT index () () ())
)
; For those who don't like typing.
; FIXME: dno?
(define-pmacro dnop
"Shorthand form of define-normal-operand.\n"
define-normal-operand
)
(define-pmacro (dndo x-name x-mode x-args
x-syntax x-base-ifield x-encoding x-ifield-assertion
x-getter x-setter)
"Define a normal derived operand."
(define-derived-operand
(name x-name)
(mode x-mode)
(args x-args)
(syntax x-syntax)
(base-ifield x-base-ifield)
(encoding x-encoding)
(ifield-assertion x-ifield-assertion)
(getter x-getter)
(setter x-setter)
)
)
; Instructions.
; Define an instruction object, normal version.
; At present all fields must be specified.
; Fields ifield-assertion is absent.
(define-pmacro (define-normal-insn name comment attrs syntax fmt semantics timing)
"Define a normal instruction.\n"
(define-full-insn name comment attrs syntax fmt () semantics timing)
)
; To reduce the amount of typing.
; Note that this is the same name as the D'ni in MYST. Oooohhhh.....
; this must be the right way to go. :-)
(define-pmacro dni
"Shorthand form of define-normal-insn.\n"
define-normal-insn
)
; Macro instructions.
; Define a macro-insn object, normal version.
; This only supports expanding to one real insn.
(define-pmacro (define-normal-macro-insn name comment attrs syntax expansion)
"Define a normal macro instruction.\n"
(define-full-minsn name comment attrs syntax expansion)
)
; To reduce the amount of typing.
(define-pmacro dnmi
"Shorthand form of define-normal-macro-insn.\n"
define-normal-macro-insn
)
; Modes.
; ??? Not currently available for use.
;
; Define Normal Mode
;
;(define-pmacro (define-normal-mode name comment attrs bits bytes
; non-mode-c-type printf-type sem-mode ptr-to host?)
; "Define a normal mode.\n"
; (define-full-mode name comment attrs bits bytes
; non-mode-c-type printf-type sem-mode ptr-to host?)
;)
;
; For those who don't like typing.
;(define-pmacro dnm
; "Shorthand form of define-normal-mode.\n"
; define-normal-mode
;)