diff --git a/app-emulation/qemu/patches/qemu-8.0.5-backports.patchset b/app-emulation/qemu/patches/qemu-8.0.5-backports.patchset new file mode 100644 index 000000000..3434c7d71 --- /dev/null +++ b/app-emulation/qemu/patches/qemu-8.0.5-backports.patchset @@ -0,0 +1,158 @@ +From 6678ed6484b25a1147af81d79386a213cfa8ae72 Mon Sep 17 00:00:00 2001 +From: Paolo Bonzini +Date: Tue, 29 Aug 2023 18:25:46 +0200 +Subject: target/i386: generalize operand size "ph" for use in CVTPS2PD + +CVTPS2PD only loads a half-register for memory, like CVTPH2PS. It can +reuse the "ph" packed half-precision size to load a half-register, +but rename it to "xh" because it is now a variation of "x" (it is not +used only for half-precision values). + +Signed-off-by: Paolo Bonzini + +diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc +index e7fa5e9458..42be3fd779 100644 +--- a/target/i386/tcg/decode-new.c.inc ++++ b/target/i386/tcg/decode-new.c.inc +@@ -337,7 +337,7 @@ static const X86OpEntry opcodes_0F38_00toEF[240] = { + [0x07] = X86_OP_ENTRY3(PHSUBSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66), + + [0x10] = X86_OP_ENTRY2(PBLENDVB, V,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66), +- [0x13] = X86_OP_ENTRY2(VCVTPH2PS, V,x, W,ph, vex11 cpuid(F16C) p_66), ++ [0x13] = X86_OP_ENTRY2(VCVTPH2PS, V,x, W,xh, vex11 cpuid(F16C) p_66), + [0x14] = X86_OP_ENTRY2(BLENDVPS, V,x, W,x, vex4 cpuid(SSE41) p_66), + [0x15] = X86_OP_ENTRY2(BLENDVPD, V,x, W,x, vex4 cpuid(SSE41) p_66), + /* Listed incorrectly as type 4 */ +@@ -565,7 +565,7 @@ static const X86OpEntry opcodes_0F3A[256] = { + [0x15] = X86_OP_ENTRY3(PEXTRW, E,w, V,dq, I,b, vex5 cpuid(SSE41) zext0 p_66), + [0x16] = X86_OP_ENTRY3(PEXTR, E,y, V,dq, I,b, vex5 cpuid(SSE41) p_66), + [0x17] = X86_OP_ENTRY3(VEXTRACTPS, E,d, V,dq, I,b, vex5 cpuid(SSE41) p_66), +- [0x1d] = X86_OP_ENTRY3(VCVTPS2PH, W,ph, V,x, I,b, vex11 cpuid(F16C) p_66), ++ [0x1d] = X86_OP_ENTRY3(VCVTPS2PH, W,xh, V,x, I,b, vex11 cpuid(F16C) p_66), + + [0x20] = X86_OP_ENTRY4(PINSRB, V,dq, H,dq, E,b, vex5 cpuid(SSE41) zext2 p_66), + [0x21] = X86_OP_GROUP0(VINSERTPS), +@@ -1103,7 +1103,7 @@ static bool decode_op_size(DisasContext *s, X86OpEntry *e, X86OpSize size, MemOp + *ot = s->vex_l ? MO_256 : MO_128; + return true; + +- case X86_SIZE_ph: /* SSE/AVX packed half precision */ ++ case X86_SIZE_xh: /* SSE/AVX packed half register */ + *ot = s->vex_l ? MO_128 : MO_64; + return true; + +diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h +index cb6b8bcf67..a542ec1681 100644 +--- a/target/i386/tcg/decode-new.h ++++ b/target/i386/tcg/decode-new.h +@@ -92,7 +92,7 @@ typedef enum X86OpSize { + /* Custom */ + X86_SIZE_d64, + X86_SIZE_f64, +- X86_SIZE_ph, /* SSE/AVX packed half precision */ ++ X86_SIZE_xh, /* SSE/AVX packed half register */ + } X86OpSize; + + typedef enum X86CPUIDFeature { +-- +2.42.0 + + +From 692d97a57c4bab09b28ce6c3fafe4a293b69a1c4 Mon Sep 17 00:00:00 2001 +From: Paolo Bonzini +Date: Tue, 29 Aug 2023 18:28:33 +0200 +Subject: target/i386: fix memory operand size for CVTPS2PD + +CVTPS2PD only loads a half-register for memory, unlike the other +operations under 0x0F 0x5A. "Unpack" the group into separate +emission functions instead of using gen_unary_fp_sse. + +Signed-off-by: Paolo Bonzini + +diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc +index 42be3fd779..93e19d3564 100644 +--- a/target/i386/tcg/decode-new.c.inc ++++ b/target/i386/tcg/decode-new.c.inc +@@ -804,10 +804,20 @@ static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entr + case 0x51: entry->gen = gen_VSQRT; break; + case 0x52: entry->gen = gen_VRSQRT; break; + case 0x53: entry->gen = gen_VRCP; break; +- case 0x5A: entry->gen = gen_VCVTfp2fp; break; + } + } + ++static void decode_0F5A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) ++{ ++ static const X86OpEntry opcodes_0F5A[4] = { ++ X86_OP_ENTRY2(VCVTPS2PD, V,x, W,xh, vex2), /* VCVTPS2PD */ ++ X86_OP_ENTRY2(VCVTPD2PS, V,x, W,x, vex2), /* VCVTPD2PS */ ++ X86_OP_ENTRY3(VCVTSS2SD, V,x, H,x, W,x, vex2_rep3), /* VCVTSS2SD */ ++ X86_OP_ENTRY3(VCVTSD2SS, V,x, H,x, W,x, vex2_rep3), /* VCVTSD2SS */ ++ }; ++ *entry = *decode_by_prefix(s, opcodes_0F5A); ++} ++ + static void decode_0F5B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b) + { + static const X86OpEntry opcodes_0F5B[4] = { +@@ -890,7 +900,7 @@ static const X86OpEntry opcodes_0F[256] = { + + [0x58] = X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), + [0x59] = X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), +- [0x5a] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), ++ [0x5a] = X86_OP_GROUP0(0F5A), + [0x5b] = X86_OP_GROUP0(0F5B), + [0x5c] = X86_OP_ENTRY3(VSUB, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), + [0x5d] = X86_OP_ENTRY3(VMIN, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), +diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc +index 4fe8dec427..45a3e55cbf 100644 +--- a/target/i386/tcg/emit.c.inc ++++ b/target/i386/tcg/emit.c.inc +@@ -1914,12 +1914,22 @@ static void gen_VCOMI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) + set_cc_op(s, CC_OP_EFLAGS); + } + +-static void gen_VCVTfp2fp(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) ++static void gen_VCVTPD2PS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) + { +- gen_unary_fp_sse(s, env, decode, +- gen_helper_cvtpd2ps_xmm, gen_helper_cvtps2pd_xmm, +- gen_helper_cvtpd2ps_ymm, gen_helper_cvtps2pd_ymm, +- gen_helper_cvtsd2ss, gen_helper_cvtss2sd); ++ if (s->vex_l) { ++ gen_helper_cvtpd2ps_ymm(cpu_env, OP_PTR0, OP_PTR2); ++ } else { ++ gen_helper_cvtpd2ps_xmm(cpu_env, OP_PTR0, OP_PTR2); ++ } ++} ++ ++static void gen_VCVTPS2PD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) ++{ ++ if (s->vex_l) { ++ gen_helper_cvtps2pd_ymm(cpu_env, OP_PTR0, OP_PTR2); ++ } else { ++ gen_helper_cvtps2pd_xmm(cpu_env, OP_PTR0, OP_PTR2); ++ } + } + + static void gen_VCVTPS2PH(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +@@ -1936,6 +1946,16 @@ static void gen_VCVTPS2PH(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec + } + } + ++static void gen_VCVTSD2SS(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) ++{ ++ gen_helper_cvtsd2ss(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); ++} ++ ++static void gen_VCVTSS2SD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) ++{ ++ gen_helper_cvtss2sd(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); ++} ++ + static void gen_VCVTSI2Sx(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) + { + int vec_len = vector_len(s, decode); +-- +2.42.0 + diff --git a/app-emulation/qemu/qemu-8.0.5.recipe b/app-emulation/qemu/qemu-8.0.5.recipe index 689730d96..47fb49ec0 100644 --- a/app-emulation/qemu/qemu-8.0.5.recipe +++ b/app-emulation/qemu/qemu-8.0.5.recipe @@ -7,12 +7,13 @@ achieves very good performance." HOMEPAGE="https://www.qemu.org/" COPYRIGHT="2003-2023 Fabrice Bellard" LICENSE="GNU GPL v2" -REVISION="1" +REVISION="2" SOURCE_URI="https://download.qemu.org/qemu-$portVersion.tar.xz" CHECKSUM_SHA256="91d3024d51e441c235dcb1b0c87cb3aab302283166e8d3d5f8282aa06c346be1" SOURCE_DIR="qemu-$portVersion" PATCHES=" qemu-$portVersion.patchset + qemu-$portVersion-backports.patchset qemu-$portVersion-haiku.patchset " ADDITIONAL_FILES="qemu.rdef.in"