haikuprojects/haikuports
1
0
Fork 0
mirror of https://github.com/yann64/haikuports.git synced 2026-05-05 06:28:55 +02:00
Code Issues Packages Projects Releases Wiki Activity

De-lint recipes.

Browse Source 
*	v8
	Removed "." from SUMMARY.
	Re-ordered blocks.

*	verilator
	80-char limit of DESCRIPTION.
	Re-ordered blocks.

*	vim
	Removed "." from SUMMARY.
	Re-ordered blocks.

*	virtulbelive
	Removed "." from SUMMARY.
	Re-ordered blocks.

*	vl_gothic
	Shortened SUMMARY.
	Re-ordered blocks.

*	vlc
	Re-ordered blocks.
	Changed libgpg-error to libgpg_error.

*	vncserver
	Improved COPYRIGHT.
	Re-ordered blocks.

*	vwget
	Removed "." from SUMMARY.
	Re-ordered blocks.

*	wesnoth
	Removed "." from SUMMARY.
	Re-ordered blocks.

*	xerces
	Removed "." from SUMMARY.
	Re-ordered blocks.

*	zip
	Re-ordered blocks.
	Lint warning of non-declared patch can be ignored, as it doesn't
	grok: $portName-$portVersion.patchset
This commit is contained in:
Humdinger
2015-07-23 13:23:17 +02:00
parent effe88db3f
commit 9e304a2e9a
14 changed files with 206 additions and 224 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
sci-electronics/verilator/verilator-3.864.recipe
View File

@@ -1,16 +1,21 @@
SUMMARY="A fast C++ Verilog simulator"
DESCRIPTION="
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
"
DESCRIPTION="Verilator is the fastest free Verilog HDL simulator, and \
beats most commercial simulators. It compiles synthesizable Verilog (not \
test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions \
into C++ or SystemC code. It is designed for large projects where fast \
simulation performance is of primary concern, and is especially well suited \
to generate executable models of CPUs for embedded software design teams."
HOMEPAGE="http://www.veripool.org/wiki/verilator"
COPYRIGHT="2006-2014 Wilson Snyder"
LICENSE="GNU GPL v3"
REVISION="2"
SOURCE_URI="http://www.veripool.org/ftp/verilator-3.864.tgz"
CHECKSUM_SHA256="f6734c2aa33946357d5abfd9211b4206297f9adf07dfc3186cbbba0d8c8842af"
REVISION="2"
PATCHES="verilator-$portVersion.patchset"
ARCHITECTURES="x86_gcc2 x86"
SECONDARY_ARCHITECTURES="x86"
PATCHES="verilator-$portVersion.patchset"
PROVIDES="
verilator$secondaryArchSuffix = $portVersion
cmd:verilator$secondaryArchSuffix
@@ -18,13 +23,14 @@ PROVIDES="
cmd:verilator_bin_dbg$secondaryArchSuffix
cmd:verilator_profcfunc$secondaryArchSuffix
"
REQUIRES="
haiku$secondaryArchSuffix
"
BUILD_PREREQUIRES="
BUILD_REQUIRES="
haiku${secondaryArchSuffix}_devel
"
BUILD_PREREQUIRES="
cmd:gcc$secondaryArchSuffix
cmd:perl
cmd:bison
@@ -48,6 +54,3 @@ TEST()
{
make check
}
LICENSE="GNU GPL v3"
COPYRIGHT="Copyright 2006-2014 by Wilson Snyder"