From a6bcca17c3086b73be114f7d0b369d06145c2d21 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Duval?= Date: Wed, 30 May 2018 08:11:41 +0200 Subject: [PATCH] verilator: update HOMEPAGE. --- sci-electronics/verilator/verilator-3.864.recipe | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sci-electronics/verilator/verilator-3.864.recipe b/sci-electronics/verilator/verilator-3.864.recipe index 313f8bbae..6322b45f1 100644 --- a/sci-electronics/verilator/verilator-3.864.recipe +++ b/sci-electronics/verilator/verilator-3.864.recipe @@ -5,10 +5,10 @@ test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions \ into C++ or SystemC code. It is designed for large projects where fast \ simulation performance is of primary concern, and is especially well suited \ to generate executable models of CPUs for embedded software design teams." -HOMEPAGE="http://www.veripool.org/wiki/verilator" +HOMEPAGE="https://www.veripool.org/wiki/verilator" COPYRIGHT="2006-2014 Wilson Snyder" LICENSE="GNU GPL v3" -REVISION="2" +REVISION="3" SOURCE_URI="http://www.veripool.org/ftp/verilator-3.864.tgz" CHECKSUM_SHA256="f6734c2aa33946357d5abfd9211b4206297f9adf07dfc3186cbbba0d8c8842af" PATCHES="verilator-$portVersion.patchset"