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Rename SRC_URI/SRC_FILENAME to SOURCE_URI/SOURCE_FILENAME.

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Augustin Cavalier
2015-07-02 11:12:32 -04:00
parent 827ec2dcbc
commit f561efbc96
1450 changed files with 1674 additions and 1674 deletions
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sci-electronics/verilator/verilator-3.864.recipe
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@@ -3,7 +3,7 @@ DESCRIPTION="
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
"
HOMEPAGE="http://www.veripool.org/wiki/verilator"
SRC_URI="http://www.veripool.org/ftp/verilator-3.864.tgz"
SOURCE_URI="http://www.veripool.org/ftp/verilator-3.864.tgz"
CHECKSUM_SHA256="f6734c2aa33946357d5abfd9211b4206297f9adf07dfc3186cbbba0d8c8842af"
REVISION="2"
ARCHITECTURES="x86_gcc2 x86"