* Move current_mode into the accelerant as the
driver doesn't care.
* Record panel_mode in driver and present to accelerant
* eDP, if no EDID and mobile, leave edid incomplete.
Mode set should notice that and fall back to panel_mode
* DisplayPort != DigitalPort
* i2c needs wrapped in DP AUX transaction code
* Mode-setting comes with DP link training as well
* We need to try and share DP code with radeon_hd
* polarity regs move on LVDS vs analog
* add knowledge or transcoder registers, they
exist seperately on PCH-split
* Native resolutions now work on LVDS under i965
* IvyBridge or higher can auto-train.
* Linux doesn't use this feature, however
manual FDI link training is *really*
complex... lets try auto-training first.
* I really hope we can kill head_mode some day
* Break pll code out from mode code
* The LVDS and Digital are smooshed together and
likely need broken apart.
* No impact to non-ValleyView chipsets
* Bump some register locations for VLV
* Only have HDMI port to test with on my ValleyView GPU
and our driver seems to be missing all HDMI and
sideband functionality.
* As ValleyView chipsets seem to be UEFI only, we don't
have VESA fallback, so this shouldn't cause regressions.
(unless we get UEFI framebuffer support)
Intel changed the PCH interrupt bits between Sandy Bridge and Ivy Bridge
to make space for the 3rd display pipe. Take this into account and check
for the correct bits on the newer devices.
Fixes #11522.
https://github.com/druga/haiku-stuff/tree/master/intel_extreme
Rebased against current sources.
* The BIOS video mode sometimes reports a scaled mode instead of the
physical panel dimensions. Get the data from the VBT table as well, and
use it if the reported resolution is bigger.
* On first boot, force the panel native mode so the user doesn't have to
set it manually.
* Only allow a single head at a time on i855gm, as the card can't drive
both heads at the same time.
* Detect when a new requested mode is the same as the current one, and
skip modesetting in that case. Avoids screen flickering when changing
workspaces.
* Fix some cases of misdetecting which pipes to enable
(they are actually reversed), so introduce a find_reg() inline function to map
such regs individually instead. Should fix interrupt storms on SandyBridge.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42870 a95241bf-73f2-0310-859d-f6bbb57e9c96
* Also add the definitions and some specifics for IronLake (ILK), but keep the
IDs disabled as at least the one version I can test with doesn't work yet.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42869 a95241bf-73f2-0310-859d-f6bbb57e9c96
* Make the pointer style consistent accross all components, which should make it
easier when working all over the place.
* 80 char limits.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42863 a95241bf-73f2-0310-859d-f6bbb57e9c96
control block. Doesn't matter on (G)MCH (they are the same register block tehre)
but fixes mode setting on PCH again.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42862 a95241bf-73f2-0310-859d-f6bbb57e9c96
register blocks and we encode their block into the register definition. On
register access these blocks are then translated into the final address.
* Set up the register blocks for (G)MCH and PCH variants.
* Remove most SandyBridge code that was actually PCH specific and is now taken
care of automatically.
* This will temporarily break SandyBridge support again until the right
transcoders are actually programmed.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42857 a95241bf-73f2-0310-859d-f6bbb57e9c96
