mirror of
https://review.haiku-os.org/haiku
synced 2025-02-01 03:06:08 +01:00
83f755b5d8
Introduce memory barriers according to ARMARM, section G.5.3 TLB maintenance operations and barriers Sequence for mapping memory in (both L1 and L2): * DSB * Invalidate i-cache (TODO) * Insert new entry in page directory / page table * DSB * ISB Sequence for mapping memory out: * Remove page table entry * DSB * Invalidate TLB entry * DSB * ISB Sequence for updating a page table entry: * Update page table entry * DSB * Invalidate TLB entry * Invalidate branch predictor (TODO) * DSB * ISB Note: i-cache invalidation and branch predictor invalidation is not implemented yet as this commit focuses on implementing memory barriers. Change-Id: I192fa80f6b43117236a4be6fa8c988afca90e015 Reviewed-on: https://review.haiku-os.org/c/haiku/+/5241 Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org> Reviewed-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>