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Verilator: Fix incorrect static -lm in makefile include

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Alexander von Gluck IV
2014-10-23 19:20:16 +00:00
parent 09c6f4743e
commit 057164b245
2 changed files with 43 additions and 1 deletions
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sci-electronics/verilator/verilator-3.864.recipe
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@@ -5,7 +5,7 @@ Verilator is the fastest free Verilog HDL simulator, and beats most commercial s
HOMEPAGE="http://www.veripool.org/wiki/verilator"
SRC_URI="http://www.veripool.org/ftp/verilator-3.864.tgz"
CHECKSUM_SHA256="f6734c2aa33946357d5abfd9211b4206297f9adf07dfc3186cbbba0d8c8842af"
REVISION="1"
REVISION="2"
ARCHITECTURES="x86_gcc2 x86"
SECONDARY_ARCHITECTURES="x86"