verilator: New Recipe, latest version.

* A Verilog to C++ compiler for simulation of FPGA and CPLD
  gate logic

sci-electronics/verilator/patches/verilator-3.864.patchset

@@ -0,0 +1,52 @@
+From 45be9ebce2e7be9683240e2ae1c720f79643c1c2 Mon Sep 17 00:00:00 2001
+From: Alexander von Gluck IV <kallisti5@unixzen.com>
+Date: Thu, 23 Oct 2014 18:35:32 +0000
+Subject: [PATCH] Haiku: Add strings.h for strcasecmp
+
+* Drop static -lm
+---
+ src/Makefile_obj.in | 2 +-
+ src/V3Error.cpp     | 1 +
+ src/V3Options.cpp   | 1 +
+ 3 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in
+index 57685d9..6a3044e 100644
+--- a/src/Makefile_obj.in
++++ b/src/Makefile_obj.in
+@@ -85,7 +85,7 @@ endif
+ #CCMALLOC = /usr/local/lib/ccmalloc-gcc.o -lccmalloc -ldl
+ 
+ # -lfl not needed as Flex invoked with %nowrap option
+-LIBS = -lm
++LIBS =
+ 
+ CPPFLAGS += -MMD
+ CPPFLAGS += -I. -I$(bldsrc) -I$(srcdir) -I$(incdir)
+diff --git a/src/V3Error.cpp b/src/V3Error.cpp
+index 8eb7c56..c907c64 100644
+--- a/src/V3Error.cpp
++++ b/src/V3Error.cpp
+@@ -21,6 +21,7 @@
+ #include <cstdio>
+ #include <cstdarg>
+ #include <cstring>
++#include <strings.h>
+ #include <set>
+ #include "V3Error.h"
+ #ifndef _V3ERROR_NO_GLOBAL_
+diff --git a/src/V3Options.cpp b/src/V3Options.cpp
+index 7c31676..85cf301 100644
+--- a/src/V3Options.cpp
++++ b/src/V3Options.cpp
+@@ -29,6 +29,7 @@
+ #include <dirent.h>
+ #include <unistd.h>
+ #include <fcntl.h>
++#include <strings.h>
+ #include <set>
+ #include <list>
+ #include <map>
+-- 
+1.8.3.4
+

sci-electronics/verilator/verilator-3.864.recipe

@@ -0,0 +1,53 @@
+SUMMARY="A fast C++ Verilog simulator"
+DESCRIPTION="
+Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
+"
+HOMEPAGE="http://www.veripool.org/wiki/verilator"
+SRC_URI="http://www.veripool.org/ftp/verilator-3.864.tgz"
+CHECKSUM_SHA256="f6734c2aa33946357d5abfd9211b4206297f9adf07dfc3186cbbba0d8c8842af"
+REVISION="1"
+ARCHITECTURES="x86_gcc2 x86"
+SECONDARY_ARCHITECTURES="x86"
+
+PATCHES="verilator-$portVersion.patchset"
+
+PROVIDES="
+	verilator$secondaryArchSuffix = $portVersion
+	cmd:verilator$secondaryArchSuffix
+	cmd:verilator_bin$secondaryArchSuffix
+	cmd:verilator_bin_dbg$secondaryArchSuffix
+	cmd:verilator_profcfunc$secondaryArchSuffix
+	"
+
+REQUIRES="
+	haiku$secondaryArchSuffix >= $haikuVersion
+	"
+
+BUILD_PREREQUIRES="
+	haiku${secondaryArchSuffix}_devel >= $haikuVersion
+	cmd:gcc$secondaryArchSuffix
+	cmd:perl
+	cmd:bison
+	cmd:flex
+	cmd:make
+	cmd:awk
+	"
+
+BUILD()
+{
+	runConfigure ./configure
+	make $jobArgs
+}
+
+INSTALL()
+{
+	make install
+}
+
+TEST()
+{
+	make check
+}
+
+LICENSE="GNU GPL v3"
+COPYRIGHT="Copyright 2006-2014 by Wilson Snyder"