verilator: New Recipe, latest version.

* A Verilog to C++ compiler for simulation of FPGA and CPLD
  gate logic

sci-electronics/verilator/verilator-3.864.recipe

@@ -0,0 +1,53 @@
+SUMMARY="A fast C++ Verilog simulator"
+DESCRIPTION="
+Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
+"
+HOMEPAGE="http://www.veripool.org/wiki/verilator"
+SRC_URI="http://www.veripool.org/ftp/verilator-3.864.tgz"
+CHECKSUM_SHA256="f6734c2aa33946357d5abfd9211b4206297f9adf07dfc3186cbbba0d8c8842af"
+REVISION="1"
+ARCHITECTURES="x86_gcc2 x86"
+SECONDARY_ARCHITECTURES="x86"
+
+PATCHES="verilator-$portVersion.patchset"
+
+PROVIDES="
+	verilator$secondaryArchSuffix = $portVersion
+	cmd:verilator$secondaryArchSuffix
+	cmd:verilator_bin$secondaryArchSuffix
+	cmd:verilator_bin_dbg$secondaryArchSuffix
+	cmd:verilator_profcfunc$secondaryArchSuffix
+	"
+
+REQUIRES="
+	haiku$secondaryArchSuffix >= $haikuVersion
+	"
+
+BUILD_PREREQUIRES="
+	haiku${secondaryArchSuffix}_devel >= $haikuVersion
+	cmd:gcc$secondaryArchSuffix
+	cmd:perl
+	cmd:bison
+	cmd:flex
+	cmd:make
+	cmd:awk
+	"
+
+BUILD()
+{
+	runConfigure ./configure
+	make $jobArgs
+}
+
+INSTALL()
+{
+	make install
+}
+
+TEST()
+{
+	make check
+}
+
+LICENSE="GNU GPL v3"
+COPYRIGHT="Copyright 2006-2014 by Wilson Snyder"