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verilator: update HOMEPAGE.

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Jérôme Duval
2018-05-30 08:11:41 +02:00
committed by GitHub
parent 376c439f16
commit a6bcca17c3
1 changed files with 2 additions and 2 deletions
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sci-electronics/verilator/verilator-3.864.recipe
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@@ -5,10 +5,10 @@ test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions \
into C++ or SystemC code. It is designed for large projects where fast \
simulation performance is of primary concern, and is especially well suited \
to generate executable models of CPUs for embedded software design teams."
HOMEPAGE="http://www.veripool.org/wiki/verilator"
HOMEPAGE="https://www.veripool.org/wiki/verilator"
COPYRIGHT="2006-2014 Wilson Snyder"
LICENSE="GNU GPL v3"
REVISION="2"
REVISION="3"
SOURCE_URI="http://www.veripool.org/ftp/verilator-3.864.tgz"
CHECKSUM_SHA256="f6734c2aa33946357d5abfd9211b4206297f9adf07dfc3186cbbba0d8c8842af"
PATCHES="verilator-$portVersion.patchset"